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Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95最新文献

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The dual-gate BRT 双门快速公交
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515004
R. Kurlagunda, B. J. Baliga
{"title":"The dual-gate BRT","authors":"R. Kurlagunda, B. J. Baliga","doi":"10.1109/ISPSD.1995.515004","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515004","url":null,"abstract":"In this paper, a new device concept called the Dual-Gate Base Resistance controlled Thyristor (DG-BRT) is reported. The DG-BRT combines the low forward drop characteristic of MOS-gated thyristors with a good forward biased safe operating area (FBSOA). When positive bias is applied to both gates, the DG-BRT operates in the thyristor mode allowing current conduction with a low forward voltage drop. When one gate is biased positive and the other negative, the DG-BRT can saturate current to high voltages. Results of two-dimensional numerical simulations and measurements performed on devices with forward blocking of 600 V are presented here.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115195690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An intelligent power device using poly-Si sandwiched wafer bonding technique 一种采用多晶硅夹片键合技术的智能电源器件
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515009
K. Kobayashi, T. Hamajima, H. Kikuchi, M. Takahashi, K. Arai
{"title":"An intelligent power device using poly-Si sandwiched wafer bonding technique","authors":"K. Kobayashi, T. Hamajima, H. Kikuchi, M. Takahashi, K. Arai","doi":"10.1109/ISPSD.1995.515009","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515009","url":null,"abstract":"A new simple isolation structure has been realized by using poly-Si sandwiched wafer bonding technique. We confirmed that the poly-Si layer enabled the bonded interface to be void-free and electrically perfect, and had the effect that it enabled the reverse recovery time of the parasitic diode of Vertical DMOSFET (VDMOS) to be short. In the new structure, the isolation capabilities were adequate to integrate 60 V VDMOS and control circuits on the same chip. Especially, the parasitic bipolar action has been suppressed. We evaluated an intelligent power device which uses this technique and have confirmed the availability of the new isolation structure.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129354222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A physically based DMOS transistor model implemented in SPICE for advanced power IC TCAD 在SPICE中实现了一种基于物理的DMOS晶体管模型，用于高级功率IC TCAD
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515061
Yeonbae Chung, D. Burk
{"title":"A physically based DMOS transistor model implemented in SPICE for advanced power IC TCAD","authors":"Yeonbae Chung, D. Burk","doi":"10.1109/ISPSD.1995.515061","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515061","url":null,"abstract":"A physics-based predictive semi-numerical lateral DMOS transistor model, which is directly implemented in commercially available SPICE2G.6 source code, is described and verified with experimental measurements. Different from the existing power device subcircuit models, our model has an ability to account for the unique device structure such as the graded-channel and the non-planar-drift region. With an advantage of directly using device and process parameters, the new model implemented in SPICE may be useful in computer-aided power IC design.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129272208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Future role of power electronics in power systems 电力电子在电力系统中的未来作用
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515001
N. Hingorani
{"title":"Future role of power electronics in power systems","authors":"N. Hingorani","doi":"10.1109/ISPSD.1995.515001","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515001","url":null,"abstract":"Power electronics is in the early stages of significant technological opportunities which will greatly enhance the role and value of electricity in all aspects from generation to the end of use. Power electronics represents an enabling means in enhancing the role and value of electricity. The basic functions of importance for power electronics are (1) power conversion, ac to dc, dc to ac, ac to ac, (2) power conditioning to remove distortion, harmonics, voltage dips and overvoltages, (3) high speed and/or frequent control of electrical parameters such as currents, voltage impedance, and phase angle, and (4) high speed and/or frequent circuit interruption transfer, and current limiting functions.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129599786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
The modified HSINFET using the trenched JBS injector 改进型HSINFET采用沟槽式JBS注入器
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515043
Han-soo Kim, Jae-Hyung Kim, Byeong-hoon Lee, M. Han, Seung-Youp Han, Yearn-Ik Choi, Sang-Koo Chung
{"title":"The modified HSINFET using the trenched JBS injector","authors":"Han-soo Kim, Jae-Hyung Kim, Byeong-hoon Lee, M. Han, Seung-Youp Han, Yearn-Ik Choi, Sang-Koo Chung","doi":"10.1109/ISPSD.1995.515043","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515043","url":null,"abstract":"A Hybrid Schottky INjector Field Effect Transistor (HSINFET) which increases the forward conduction current without sacrificing the latch-up capability and turn-off characteristics, is proposed. The feature of the structure is that the hybrid Schottky injector is implemented by the trench sidewall Schottky contact and p-n junction injector at the bottom of a trench. The device characteristics of the proposed HSINFET are numerically simulated and compared with conventional devices. The proposed HSINFET exhibits a lower forward voltage drop than the conventional HSINFET by 0.4 V at 100 A/cm/sup 2/.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131133632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Theoretical and experimental investigation of 500 V p- and n-channel VDMOS-LIGBT transistors 500v p沟道和n沟道vdmos - light晶体管的理论和实验研究
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515042
V. Parthasarathy, T. Chow
{"title":"Theoretical and experimental investigation of 500 V p- and n-channel VDMOS-LIGBT transistors","authors":"V. Parthasarathy, T. Chow","doi":"10.1109/ISPSD.1995.515042","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515042","url":null,"abstract":"Static and dynamic performance of the n-channel VDMOS-LIGBT, presented for the first time in this work, has been studied as a function of a few critical design parameters. A novel method for minimizing snap-back in this device and other similar hybrid devices is described. A unique back-injection of current out of the IGBT anode of the n-channel VDMOS-LIGBT during resistive turn-off has been observed experimentally and is elucidated using numerical simulations.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121991822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
350 V carrier injection field effect transistor (CIFET) with very low on-resistance and high switching speed 350v载流子注入场效应晶体管(CIFET)具有极低的导通电阻和高的开关速度
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515080
Y. Sugawara, M. Nemoto, Y. Nemoto, H. Akakawa
{"title":"350 V carrier injection field effect transistor (CIFET) with very low on-resistance and high switching speed","authors":"Y. Sugawara, M. Nemoto, Y. Nemoto, H. Akakawa","doi":"10.1109/ISPSD.1995.515080","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515080","url":null,"abstract":"To realize low on-state voltage and high switching speed, a new device, a CIFET (Carrier Injection Field Effect Transistor), is proposed. The fabricated 350 V lateral CIFET has a low on-state voltage of less than 0.8 V at 100 A/cm/sup 2/, which is difficult to be achieved by IGBTs, ESTs and MCTs. Its fall time is reduced to about 0.2 /spl mu/s by electron irradiation. Early removal of the injected gate current (more than 5 /spl mu/s) before removing the MOS gate voltage shortens the fall time to about 70 ns.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122019573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
1200 V, 150 A insulated-gate thyristors 1200v, 150a绝缘栅晶闸管
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515005
J. Ajit, D. Kinzer
{"title":"1200 V, 150 A insulated-gate thyristors","authors":"J. Ajit, D. Kinzer","doi":"10.1109/ISPSD.1995.515005","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515005","url":null,"abstract":"A insulated-gate thyristor (IGTH) design for achieving high controllable current capability is described. A square-cellular design with high density of MOS-channels modulating the resistance of the base region of the NPN transistor of the thyristor structure is-used. The IGTH was fabricated using a double-diffused DMOS process and 1200 V devices with controllable currents in excess of 150 A were obtained.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Low on-resistance LDMOSFETs with DSS (a drain window surrounded by source windows) pattern layout 具有DSS(漏极窗被源窗包围)模式布局的低导通ldmosfet
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515010
M. Hoshi, Y. Shimoida, Y. Hayami, T. Mihara
{"title":"Low on-resistance LDMOSFETs with DSS (a drain window surrounded by source windows) pattern layout","authors":"M. Hoshi, Y. Shimoida, Y. Hayami, T. Mihara","doi":"10.1109/ISPSD.1995.515010","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515010","url":null,"abstract":"This paper describes new low on-resistance lateral DMOSFETs having a DSS (a Drain window Surrounded by Source windows) pattern layout. The new DSS pattern layout increases the source cell density to as high as 4 million cells/inch/sup 2/ thus minimizing the channel-resistance of the devices. A specific on-resistance of 0.65 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 36 V is obtained. The DSS LDMOSFETs are suitable for intelligent power devices (IPDs) that provide multiple outputs.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"23 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Influence of a bonded interface on the DC characteristics of a high voltage bipolar transistor 键合界面对高压双极晶体管直流特性的影响
Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI: 10.1109/ISPSD.1995.515049
A. Laporte, M. Bagneres, D. Strutzenberger, J. Reynes, G. Sarrabayrouse
{"title":"Influence of a bonded interface on the DC characteristics of a high voltage bipolar transistor","authors":"A. Laporte, M. Bagneres, D. Strutzenberger, J. Reynes, G. Sarrabayrouse","doi":"10.1109/ISPSD.1995.515049","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515049","url":null,"abstract":"The bonded interface situated in an active layer of a high voltage bipolar transistor (base or collector) leads to a deterioration of the DC characteristics. The electron lifetime modification or the interfacial potential barrier due to the interfacial defects or impurities could be at the origin of these degradations.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134032870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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