Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95最新文献

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A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation 用于电路仿真的具有自加热的SOI横向DMOS器件的闭式物理后门偏置准饱和模型
C.M. Liu, F. Shone, J. Kuo
{"title":"A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation","authors":"C.M. Liu, F. Shone, J. Kuo","doi":"10.1109/ISPSD.1995.515057","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515057","url":null,"abstract":"This paper reports a closed-form physical back-gate-bias dependent quasi-saturation model for silicon-direct-bonded lateral SOI DMOS devices with self-heating. By solving Poisson's equation in the substrate direction with the thermal equation, a closed-form physical SOI DMOS quasi-saturation model considering lattice temperature suitable for circuit simulation has been derived. Based on the analytical model, the surface state above the field oxide may effectively decrease the back gate bias effect on the quasi-saturation behavior in the SOI DMOS device. With a more negative back gate bias, the thermal effect on quasi-saturation is less influential.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Simulations and measurements of emitter properties in 5 kV Si PIN diodes 5kv Si PIN二极管发射极特性的模拟与测量
O. Tornblad, M. Domeij, B. Breitholtz, J. Linnros, M. Ostling
{"title":"Simulations and measurements of emitter properties in 5 kV Si PIN diodes","authors":"O. Tornblad, M. Domeij, B. Breitholtz, J. Linnros, M. Ostling","doi":"10.1109/ISPSD.1995.515067","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515067","url":null,"abstract":"Emitter properties have been studied by comparing simulated and measured data of excess carrier concentration and surface potential in 5 kV Si PIN diodes. Comparison were made under forward conduction and turn-on for current densities in the range 30-300 A/cm/sup 2/ and for different depths and concentrations of the n/sup +/ and p/sup +/ emitters. The density of excess carriers were measured by the Free Carrier Absorption (FCA) technique as a function of depth and the surface potential by scanning a tungsten probe tip on the polished diode surfaces. The FCA measurements correlate well to simulated data, but discrepancies between simulated and measured data of the surface potential indicate the need for improved physical models.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116879525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High-efficiency performance of microwave power 4H-SiC amplifiers 微波功率4H-SiC放大器的高效率性能
M. Shin, T.J. Kordas, R. Trew
{"title":"High-efficiency performance of microwave power 4H-SiC amplifiers","authors":"M. Shin, T.J. Kordas, R. Trew","doi":"10.1109/ISPSD.1995.515088","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515088","url":null,"abstract":"The high frequency performance of a 4H-SiC MESFET is examined using an advanced harmonic-balance device/circuit simulator combined with the two-dimensional device simulator PISCES-IIB. Very good agreement with experimental measurements is achieved. Circuit and device optimizations are discussed. An improved device structure with a maximum power added efficiency approaching the theoretical limit is predicted.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123463116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 8 kV 3500 A light triggered thyristor 一个8kv 3500a光触发晶闸管
T. Nimura, Y. Tsunoda, Y. Tadokoro, N. Yamano
{"title":"A 8 kV 3500 A light triggered thyristor","authors":"T. Nimura, Y. Tsunoda, Y. Tadokoro, N. Yamano","doi":"10.1109/ISPSD.1995.515031","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515031","url":null,"abstract":"8 kV-3500 A light-triggered thyristor (LTT) has been developed using a 6 in wafer. The LTT has an improved gate structure to achieve high light triggering sensitivity, high di/dt capability and high dv/dt tolerance. Especially, trade-off between on-state voltage and reverse recovery charge has been improved by proton irradiation.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123787016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A novel rectifier based on bipolar-mode SIT structure 一种基于双极模SIT结构的新型整流器
K. Yano, M. Kasuga, A. Shimizu, M. Mitsui, H. Moroshima, J. Morita
{"title":"A novel rectifier based on bipolar-mode SIT structure","authors":"K. Yano, M. Kasuga, A. Shimizu, M. Mitsui, H. Moroshima, J. Morita","doi":"10.1109/ISPSD.1995.515048","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515048","url":null,"abstract":"The authors propose a novel rectifier based on bipolar-mode static induction transistor (BSIT) operation. A numerical simulation has revealed that, this rectifier, which operates with a combination of static induction effects and minority carrier injection during forward conduction, exhibits a forward-voltage drop and a reverse recovery time that are smaller than those of the conventional p-i-n rectifiers, and without causing excessive leakage current. It is also shown that, at temperatures below 400 K, the steady state power dissipation for the rectifier using BSIT operation is superior to that for the p-i-n rectifiers and the Schottky rectifiers.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115591985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application specific IPM for low power-end motor drives 应用特定的IPM低功率端电机驱动器
G. Majumdar, S. Hatae, M. Fukunaga, T. Oota
{"title":"Application specific IPM for low power-end motor drives","authors":"G. Majumdar, S. Hatae, M. Fukunaga, T. Oota","doi":"10.1109/ISPSD.1995.515036","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515036","url":null,"abstract":"Along with the rise of need for global energy conservation, the inverterization in the power electronics field is progressing quickly. In the area of low power motor control also, inverterization has become an indispensable choice, since it corresponds to ensuing regulations related to the Earth's energy preservation. However, in this low power area the cost of inverterization has to be justifiable and, so, optimization of total-cost-performance ratio has become very important. This time, paying attention to low capacity motor drive, a new series of intelligent power modules (IPM) called the ASIPM (Application Specific IPM) covering 0.1 kW through 1.5 kW drive capability has been developed. These devices contribute further miniaturization and higher performance features to its application systems. As these devices have been developed through various process of optimization related to IGBT chip, free-wheel diode chip, main controller HVIC circuitry and process technologies, packaging structure, etc., these promise high-level cost-to-performance feature to the next generation application systems. This paper explains the aspects of internal system design and key-technologies involved together with numerous functions and features of the new ASIPM series.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"286 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124553790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Subcircuit SPICE modeling of a lateral IGBT for high voltage power IC design 用于高压功率集成电路设计的横向IGBT子电路SPICE建模
Y. Kawaguchi, Y. Terazaki, A. Nakagawa
{"title":"Subcircuit SPICE modeling of a lateral IGBT for high voltage power IC design","authors":"Y. Kawaguchi, Y. Terazaki, A. Nakagawa","doi":"10.1109/ISPSD.1995.515062","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515062","url":null,"abstract":"In this paper, a subcircuit model of lateral IGBTs on SOI substrate for SPICE simulation is presented. The model accurately takes into account the characteristics of lateral IGBTs based on the results of 2-D device simulators. Static and transient analysis of a lateral IGBT was carried out, using this model. The simulation results agreed very well with experimental results. An application of the proposed model to a over current protection circuit design is presented.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124790872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The ES-MGBT: a new fast switching MOS-gated power bipolar transistor with conductivity-modulation by a positive feedback mechanism ES-MGBT是一种新型快速开关mos门控功率双极晶体管,其电导率由正反馈机制调制
J. Ajit, D. Kinzer
{"title":"The ES-MGBT: a new fast switching MOS-gated power bipolar transistor with conductivity-modulation by a positive feedback mechanism","authors":"J. Ajit, D. Kinzer","doi":"10.1109/ISPSD.1995.515027","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515027","url":null,"abstract":"A new MOS-gated device structure called the ES-MGBT is described which consists of P/sup +/ and N/sup +/ emitters, both of which are in emitter-switched configuration. In the ES-MGBT, a P/sup +/ injector coupled to the drain potential by a vertical driver DMOSFET is used to inject holes. A novel cell design is used to divert the injected holes to conductivity modulate the driver DMOSFET resulting in a low on-state voltage drop by a positive feedback mechanism. In addition, the bipolar transistor components of the device are placed in an emitter-switched configuration by the cell design which results in fast switching, high avalanche capability, and fully gate controlled characteristics. 750 V ES-MGBT devices fabricated along with DMOSFET devices on the same wafer showed 25% improvement in current density at room temperature and 36% improvement at 75/spl deg/C at a forward drop of 3.5 V. The turn-off time of the ES-MGBT was 80 ns - equal to that of the DMOSFET.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130482428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
4500 V IEGTs having switching characteristics superior to GTO 具有优于GTO的开关特性的4500v晶体管
M. Kitagawa, A. Nakagawa, K. Matsushita, S. Hasegawa, T. Inoue, A. Yahata, H. Takenaka
{"title":"4500 V IEGTs having switching characteristics superior to GTO","authors":"M. Kitagawa, A. Nakagawa, K. Matsushita, S. Hasegawa, T. Inoue, A. Yahata, H. Takenaka","doi":"10.1109/ISPSD.1995.515086","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515086","url":null,"abstract":"In this paper, the authors report, for the first time, an exact prediction of the turn-off characteristics of 4500 V IEGTs and compare the results with those for GTOs. The prediction was made by means of device simulation and trial fabrication of IEGTs. The turn-off power loss of the 4500 V IEGT with a 17 /spl mu/m deep trench gate is predicted to be less than that of the 4500 V GTO-thyristor. It was found that the IEGTs with 4 /spl mu/m deep and wide trench gate can attain a small on-state voltage drop, which is the same level as that of the IEGT with 17 /spl mu/m deep and narrow trench gate. The on-state voltage drop of the fabricated IEGT with the 4 /spl mu/m deep trench gate is 4.5 V at 50 A/cm/sup 2/. Although the device design of the fabricated IEGT was not optimized, the observed turn-off characteristics were in good agreement with the simulated results. It has been numerically confirmed that the 4500 V IEGT can realize a smaller turn-off loss than a 4500 V GTO-thyristor under a typical application circuit. It was, thus, confirmed that IEGTs can replace GTOs without degradation of switching frequency.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133168281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A dielectric isolated high-voltage IC-technology for off-line applications 一种用于离线应用的介电隔离高压集成电路技术
M. Stoisiek, K. Oppermann, U. Schwalke, D. Takács
{"title":"A dielectric isolated high-voltage IC-technology for off-line applications","authors":"M. Stoisiek, K. Oppermann, U. Schwalke, D. Takács","doi":"10.1109/ISPSD.1995.515058","DOIUrl":"https://doi.org/10.1109/ISPSD.1995.515058","url":null,"abstract":"The paper reports a first attempt to a dielectric isolated 600 V IC-process. With commercially available direct-wafer-bonded Si/SiO/sub 2//Si-wafers we processed the isolated islands with the basic high voltage devices in a standard sub-/spl mu/ fabrication line. For the lateral isolation we used a deep trench etch- and refill process. Experimental results for lateral high voltage DMOS (LDMOS), and p-MOS transistors (HVPMOS) as well as lateral IGBTs (LIGBT) and diodes are in good agreement with the target values. The suitability of the process concept for the intended applications is shown with an IGBT half-bridge demonstrator.","PeriodicalId":200109,"journal":{"name":"Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131271164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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