A dielectric isolated high-voltage IC-technology for off-line applications

Abstract

The paper reports a first attempt to a dielectric isolated 600 V IC-process. With commercially available direct-wafer-bonded Si/SiO/sub 2//Si-wafers we processed the isolated islands with the basic high voltage devices in a standard sub-/spl mu/ fabrication line. For the lateral isolation we used a deep trench etch- and refill process. Experimental results for lateral high voltage DMOS (LDMOS), and p-MOS transistors (HVPMOS) as well as lateral IGBTs (LIGBT) and diodes are in good agreement with the target values. The suitability of the process concept for the intended applications is shown with an IGBT half-bridge demonstrator.