Low on-resistance LDMOSFETs with DSS (a drain window surrounded by source windows) pattern layout

Abstract

This paper describes new low on-resistance lateral DMOSFETs having a DSS (a Drain window Surrounded by Source windows) pattern layout. The new DSS pattern layout increases the source cell density to as high as 4 million cells/inch/sup 2/ thus minimizing the channel-resistance of the devices. A specific on-resistance of 0.65 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 36 V is obtained. The DSS LDMOSFETs are suitable for intelligent power devices (IPDs) that provide multiple outputs.