具有DSS(漏极窗被源窗包围)模式布局的低导通ldmosfet

Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95 Pub Date : 1995-05-23 DOI:10.1109/ISPSD.1995.515010

M. Hoshi, Y. Shimoida, Y. Hayami, T. Mihara

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引用次数: 3

摘要

本文描述了具有DSS(漏极窗被源窗包围)模式布局的新型低导通阻横向dmosfet。新的DSS模式布局将源单元密度提高到高达400万个单元/英寸/sup 2/，从而最大限度地减少了器件的通道电阻。电阻率为0.65 m/spl ω //spl middot/cm/sup 2/，阻塞电压为36v。DSS ldmosfet适用于提供多输出的智能功率器件(ipd)。

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Low on-resistance LDMOSFETs with DSS (a drain window surrounded by source windows) pattern layout

This paper describes new low on-resistance lateral DMOSFETs having a DSS (a Drain window Surrounded by Source windows) pattern layout. The new DSS pattern layout increases the source cell density to as high as 4 million cells/inch/sup 2/ thus minimizing the channel-resistance of the devices. A specific on-resistance of 0.65 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 36 V is obtained. The DSS LDMOSFETs are suitable for intelligent power devices (IPDs) that provide multiple outputs.

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Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95

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