IEEE Electron Device Letters最新文献

{"title":"Complementary Vertical FETs (CVFETs) Enabled by a Novel Dual-Side Process","authors":"Y. Du;Y. K. Zhang;H. L. Zhu;B. H. Wang;Q. Wang;W. L. Liu;Z. C. Wang;T. R. Luo;S. S. Lu;P. H. Sun;X. Y. Chen;Y. T. Zheng;H. Yang;J. J. Li;J. F. Li;X. L. Wang;J. Luo;W. W. Wang;B. W. Dai;T. C. Ye","doi":"10.1109/LED.2025.3587989","DOIUrl":"https://doi.org/10.1109/LED.2025.3587989","url":null,"abstract":"We demonstrated the monolithically integrated complementary vertical-channel field-effect-transistor (CVFET) inverters with an innovative dual-side process (DSP). Good electrical characteristics for both NMOS and PMOS were achieved: transconductance of <inline-formula> <tex-math>$69~mu $ </tex-math></inline-formula>S/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, <inline-formula> <tex-math>${mathrm{I}}_{text {on}} = 18~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m (@ VGS – <inline-formula> <tex-math>${mathrm{V}}_{text {T}} =0.45$ </tex-math></inline-formula> V, <inline-formula> <tex-math>${mathrm{V}}_{text {DD}}=0.65$ </tex-math></inline-formula> V), Ion/<inline-formula> <tex-math>${mathrm{I}}_{text {off}} = 3.1times 10^{{6}}$ </tex-math></inline-formula>, SS =69 mV/dec and DIBL =12 mV/V for the top NMOS, and transconductance of <inline-formula> <tex-math>$592~mu $ </tex-math></inline-formula>S/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, <inline-formula> <tex-math>${mathrm{I}}_{text {on}} = 136~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m (@ VGS – <inline-formula> <tex-math>${mathrm{V}}_{text {T}} = -0.45$ </tex-math></inline-formula> V, <inline-formula> <tex-math>${mathrm{V}}_{text {DD}}= -0.65$ </tex-math></inline-formula> V), Ion/<inline-formula> <tex-math>${mathrm{I}}_{text {off}} = 5.4times 10^{{6}}$ </tex-math></inline-formula>, SS =72 mV/dec and DIBL=18 mV/V for the bottom PMOS. The functional CVFET inverters show well-balanced voltage transfer characteristics (VTC) up to 1.2 V with a maximum gain of 13 V/V. Furthermore, the CVFETs also featured with crystal-Si vertical channels and common self-aligned high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> metal gates. The CVFET structure and its integration scheme are strong candidates for the applications of advanced logic technologies.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1473-1476"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"First Demonstration of High-Temperature Reliability on La:HZO-La:In2O3 FeFET With High Endurance of 1010 at 125 °C","authors":"Min Zeng;Shiwei Yan;Shiyuan Liu;Tianyue Fu;Qianlan Hu;Yanqing Wu","doi":"10.1109/LED.2025.3587573","DOIUrl":"https://doi.org/10.1109/LED.2025.3587573","url":null,"abstract":"In this letter, we demonstrate 8 nm and 5 nm lanthanum-doped <inline-formula> <tex-math>$Hf_{{0}.{5}}$ </tex-math></inline-formula> <inline-formula> <tex-math>$Zr_{{0}.{5}}$ </tex-math></inline-formula>O2 (La:HZO) films with excellent ferroelectric and robust reliability at high temperature for the first time. A low saturated operating voltage of 1.2 V and high breakdown field of 9 MV/cm are obtained in 5 nm La:HZO films at the same time. A high endurance of <inline-formula> <tex-math>${3}times {10} ^{{11}}$ </tex-math></inline-formula> at room temperature and <inline-formula> <tex-math>$10^{{10}}$ </tex-math></inline-formula> at high temperature of <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C is obtained in 5 nm La:HZO films, owing to the superior low Eop/Ebd. Furthermore, we demonstrate a top-gate FeFET on La:In2O3 channel with a channel length of 50 nm, demonstrating superior high endurance of <inline-formula> <tex-math>${3}times {10} ^{{11}}$ </tex-math></inline-formula> with a memory window (MW) of 0.9 V at room temperature and <inline-formula> <tex-math>$10^{{10}}$ </tex-math></inline-formula> with a memory window of 0.9 V at high temperature of <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C. Besides, our FeFETs exhibit excellent retention exceeding 10 years at <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C, showing the great potential of La:HZO for high-reliability ferroelectric applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1632-1635"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Role of Oxygen Deficiencies on the Stability of Indium Tin Oxide (ITO) Transistors","authors":"Sumaiya Wahid;Kasidit Toprasertpong;Mahnaz Islam;Aravindh Kumar;Muhammed Ahosan Ul Karim;Harsono Simka;Wong H. S. Philip;Eric Pop","doi":"10.1109/LED.2025.3587706","DOIUrl":"https://doi.org/10.1109/LED.2025.3587706","url":null,"abstract":"We investigate the threshold voltage (<inline-formula> <tex-math>${V}_{T}$ </tex-math></inline-formula>) stability of indium tin oxide (ITO) transistors under positive gate bias stress, comparing the performance of <inline-formula> <tex-math>$text{Al}_{mathbf {{2}}}text {O}_{mathbf {{3}}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$text{HfO}_{mathbf {{2}}}$ </tex-math></inline-formula> dielectrics. We attribute the unusual negative <inline-formula> <tex-math>${V} _{mathbf {T}}$ </tex-math></inline-formula> shift (<inline-formula> <tex-math>$Delta {V}_{T} lt 0$ </tex-math></inline-formula> V) of our top-gated devices to oxygen scavenging by the dielectric. Notably, devices with <inline-formula> <tex-math>$text{Al}_{mathbf {{2}}}text {O}_{mathbf {{3}}}$ </tex-math></inline-formula> dielectric achieve median <inline-formula> <tex-math>$vert Delta {V}_{T}vert le 10$ </tex-math></inline-formula> mV at room temperature, <inline-formula> <tex-math>$sim 10times $ </tex-math></inline-formula> lower than devices with <inline-formula> <tex-math>$text{HfO}_{mathbf {{2}}}$ </tex-math></inline-formula>, highlighting the significant influence of the dielectric layer. We also demonstrate that opposing effects of the top and bottom gates in a dual-gated transistor can be used to attain a median <inline-formula> <tex-math>$vert Delta {V}_{T}vert approx ~150$ </tex-math></inline-formula> mV with 2 V gate stress voltage, at elevated temperature (85°C), which is <inline-formula> <tex-math>$sim 3times $ </tex-math></inline-formula> lower than the top-gated devices under identical stress conditions.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1553-1556"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Performance β-Ga2O3 Alpha Particle Detector With 4.3% Energy Resolution","authors":"Shiyu Bai;Xiangdong Meng;Xiaohu Hou;Yuncheng Han;Zhao Han;Zhenghang Xu;Yan Liu;Lei Ren;Xiaolong Zhao;Xuanze Zhou;Guangwei Xu;Shibing Long","doi":"10.1109/LED.2025.3586879","DOIUrl":"https://doi.org/10.1109/LED.2025.3586879","url":null,"abstract":"Alpha particle detectors with high energy resolution are urgently needed in various environmental monitoring applications, basic fields of high-energy physics, and new energy development. In this work, based on NiO/<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 heterojunction diodes with mesa termination, the highest energy resolution of 4.3% for 5486 keV <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula> particles in Ga2O3 particle detectors reported so far is achieved. The high detection performance is attributed to the suppression of leakage current by the mesa structure and the alpha particle collimation scheme introduced in the test. In addition, the performance of the detector shows high stability under continuous operation. These results provide a feasible strategy for the design of high-performance Ga2O3-based ionizing radiation detectors.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1573-1576"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144916317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Total Ionizing Dose Hardening Methodology in Back Gate Embedded SOI MOSFETs With Ultrathin Buried Oxide","authors":"Yuxin Liu;Qiang Liu;Jin Chen;Wenjie Yu","doi":"10.1109/LED.2025.3587666","DOIUrl":"https://doi.org/10.1109/LED.2025.3587666","url":null,"abstract":"A novel total ionizing dose (TID) hardening method is proposed based on the innovative back gate embedded silicon on insulator (BGESOI) technology. By elaborately designing the manufacturing process, the symmetric split gate configuration is constructed within the standard CMOS platforms. Notably, the BGESOI MOSFET features ~6nm buried oxide, which is thinner than that in typical fully depleted silicon on insulator (FDSOI) devices, thereby achieving enhanced TID tolerance. The device exhibits a threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}text {)}$ </tex-math></inline-formula> shift of around -30mV @7Mrad(Si) which can be further compensated by adjusting the back gate bias by only ~80mV thanks to its ultrahigh body factor (<inline-formula> <tex-math>$ge 350$ </tex-math></inline-formula>mV/V). This work presents a promising solution for robust TID hardening in extremely harsh radiation environments.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1465-1468"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144917293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"β-Ga₂O₃ Schottky Barrier Diodes Utilizing Ammonia Plasma Surface Treatment Yield Enhanced Characteristics","authors":"Haodong Hu;Xiaole Jia;Yibo Wang;Shuqi Huang;Bochang Li;Cizhe Fang;Haiwen Xu;Xiaoxi Li;Zhengdong Luo;Yan Liu;Yue Hao;Genquan Han","doi":"10.1109/LED.2025.3587728","DOIUrl":"https://doi.org/10.1109/LED.2025.3587728","url":null,"abstract":"In this work, we demonstrate high-performance vertical <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 Schottky barrier diodes (SBDs) using ammonia plasma surface treatment (APT) and self-aligned mesa termination (MT). The APT reduces the interface trap density to <inline-formula> <tex-math>$3.6times 10^{{11}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{2}}$ </tex-math></inline-formula> eV<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>, while the MT suppresses the peak electric field at the anode edge. This combination results in a breakdown voltage of 2034 V with a specific on-resistance of 3.31 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula> cm2, achieving a high power figure of merit of 1.25 GW/cm2. The reduction of Ga-suboxide and adsorbed oxygen improves the interface quality of Ni/<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 SBDs by APT, leading to excellent forward characteristics with an ideality factor reaching 1.012. This work highlights the potential of combining APT and MT to enhance <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 SBDs for power applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1485-1488"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144917294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of p-SiGe/n-Si NSs CFET Using Single-Step Ge-Selective Etching Method and Wafer-Bonding Technique","authors":"Chun-Lin Chu;Szu-Hung Chen;Shu-Han Hsu;Guang-Li Luo;Wen-Fa Wu","doi":"10.1109/LED.2025.3587731","DOIUrl":"https://doi.org/10.1109/LED.2025.3587731","url":null,"abstract":"The fabrication of heterogeneous p-SiGe/n-Si channel CFETs presents significant challenges. In a single fin structure, selectively etching the Si layer while preserving the SiGe layer for the p-FET and selectively etching the SiGe layer while preserving the Si layer for the n-FET requires two opposite etching steps. This process becomes particularly complex because of the additional local lithography required. In this study, CFETs with multiply stacked p-SiGe/n-Si nanosheet channels by using Ge interlayers as sacrificial layers are demonstrated based on the wafer-bonding process flow.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1644-1647"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Hermetically Sealed Micro Vacuum Ultraviolet Light Source for Detection of VOCs","authors":"Weilong You;Wen Chen;Yong Xie;Sheng Liu;Guoqiang Wu","doi":"10.1109/LED.2025.3587719","DOIUrl":"https://doi.org/10.1109/LED.2025.3587719","url":null,"abstract":"Vacuum ultraviolet (VUV) light sources play a crucial role in volatile organic compounds (VOCs) detection and other analytical applications. In this letter, a hermetically sealed micro-chip with nitrogen-plasma for VUV light source is demonstrated. The designed <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>VUV light source chip is fabricated based on silicon-on-insulator platform and hermetically sealed in a ceramic carrier equipped with a chip-scale MgF2 window for VUV light transmission. To verify device performance, the fabricated <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>VUV light source chip is integrated with a commercial ionization chamber for achieving a micro photoionization detector (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>PID). Measurement results illustrate that the reported <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>VUV light source chip can emit VUV light with wavelength as low as 113.72 nm and the constructed <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>PID achieves an ionization energy up to 10.9 eV. It exhibits a superior normalized photoionization efficiency, compared with a commercial PID typically with an ionization energy of 10.6 eV. Furthermore, its leakage rate (<inline-formula> <tex-math>${1}.{5}times {10} ^{-{12}}$ </tex-math></inline-formula> atm<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula> cc/s) is three orders of magnitude lower than that of commercial VUV lamps, indicating a significantly extended operational liftime. It offers an innovative solution for high-performance VUV light source in <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>PID, which provides a promising approach for the miniaturization and portability of VOCs detection devices, gas chromatograph and other ionization-based analytical instruments.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1616-1619"},"PeriodicalIF":4.5,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"1200 V Fully-Vertical GaN-on-Si Power MOSFETs","authors":"Yuchuan Ma;Hang Chen;Shuhui Zhang;Huantao Duan;Bin Hu;Huimei Ma;Jianfei Shen;Minghua Zhu;Jin Rao;Chao Liu","doi":"10.1109/LED.2025.3586947","DOIUrl":"https://doi.org/10.1109/LED.2025.3586947","url":null,"abstract":"We report 1200 V fully-vertical GaN-on-Si trench MOSFETs with fluorine implanted termination (FIT-MOS). The FIT region with negative fixed charges becomes resistive and naturally isolates the discrete devices, replacing the conventional mesa etching termination (MET), eliminating the electric field crowding effect at the mesa edges, therefore boosting the breakdown voltage of the FIT-MOS to 1277 V from 567 V of the MET-MOS. Moreover, the as-fabricated FIT-MOS exhibits a threshold voltage (<inline-formula> <tex-math>${V}_{textit {TH}}text {)}$ </tex-math></inline-formula> of 3.3 V, an ON/OFF ratio of <inline-formula> <tex-math>$sim 10^{{7}}$ </tex-math></inline-formula>, together with a specific ON-resistance (<inline-formula> <tex-math>${R}_{textit {ON}, textit {SP}}text {)}$ </tex-math></inline-formula> of 5.6 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2. These results show great potential of cost-effective GaN-on-Si vertical transistors for kV-class applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1513-1516"},"PeriodicalIF":4.5,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient LDMOS Design via Transferable Surrogate Models and Multi-Objective Optimization","authors":"Hongyu Tang;Chenggang Xu;Xiaoyun Huang;Yuxuan Zhu;Yunlong Li;Dawei Gao;Yitao Ma;Kai Xu","doi":"10.1109/LED.2025.3586707","DOIUrl":"https://doi.org/10.1109/LED.2025.3586707","url":null,"abstract":"Optimizing LDMOS performance requires balancing breakdown voltage (BV) and specific on-resistance (<inline-formula> <tex-math>$text {R}_{text {on},text {sp}}$ </tex-math></inline-formula>) under silicon-limit constraints. Conventional technology computer-aided design (TCAD)-based device design is time-consuming and inefficient for large parameter spaces. This work presents a machine learning (ML)-assisted framework that combines initial and fine-tuned deep neural network (DNN) surrogate models with multi-objective particle swarm optimization (MOPSO). The fine-tuned DNN adapts to a non-overlapping extended design space using only a small dataset, while the two surrogates are selectively applied during MOPSO to evaluate candidate designs, enabling significantly faster design evaluation compared to TCAD. SHAP analysis reveals consistent feature importance that aligns with the underlying device physics. The framework constructs diverse Pareto-optimal fronts, offering a scalable solution for automated LDMOS optimization under complex performance trade-offs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1593-1596"},"PeriodicalIF":4.5,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}