IEEE Electron Device Letters最新文献

{"title":"IEEE Electron Device Letters Information for Authors","authors":"","doi":"10.1109/LED.2025.3526027","DOIUrl":"https://doi.org/10.1109/LED.2025.3526027","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 2","pages":"319-319"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857341","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications","authors":"","doi":"10.1109/LED.2025.3528279","DOIUrl":"https://doi.org/10.1109/LED.2025.3528279","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 2","pages":"322-323"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857359","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EDS Meetings Calendar","authors":"","doi":"10.1109/LED.2025.3526025","DOIUrl":"https://doi.org/10.1109/LED.2025.3526025","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 2","pages":"318-318"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857420","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Demonstration of 4H-SiC Charge Balance Floating Junction Barrier Schottky Diode With High Baliga Figure of Merit","authors":"Jingyu Li;Qingwen Song;Hao Yuan;Fengyu Du;Haobo Kang;Tianyu Shu;Yu Zhou;Chao Han;Xiaoyan Tang;Yuming Zhang","doi":"10.1109/LED.2025.3535678","DOIUrl":"https://doi.org/10.1109/LED.2025.3535678","url":null,"abstract":"Lower specific on-resistance (Ron,sp) and higher breakdown voltage (BV) are the primary goals of silicon carbide (SiC) power devices. This letter establishes a multi-layer floating junction device model based on charge balance theory and presents an optimized 4H-SiC floating junction Schottky barrier diode (CB-FJJBS) verified through experiments. With the utilization of charge balance theory, the device achieves a more balanced electric field(EF) distribution, thereby enhancing its breakdown characteristics. Notably, the device exhibits a Baliga figure of merit (BFOM, i.e., 4V<inline-formula> <tex-math>${_{text {B}}} {^{{2}}}$ </tex-math></inline-formula>/Ron,sp) of 12.1 GW/cm2, a Ron,sp of <inline-formula> <tex-math>${mathrm {4.9~text {m}Omega }} cdot $ </tex-math></inline-formula> cm2 and a BV of 3.85 kV, representing the best performance among reported SiC floating junction (FJ) devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"640-643"},"PeriodicalIF":4.1,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Split-p-GaN Gate HEMT With Suppressed Negative Vth Shift and Enhanced Robustness Against False Turn-On","authors":"Yunhong Lao;Jin Wei;Maojun Wang;Jingjing Yu;Zetao Fan;Junjie Yang;Jiawei Cui;Teng Li;Han Yang;Muqin Nuo;Qimeng Jiang;Gaofei Tang;Bo Shen","doi":"10.1109/LED.2025.3535601","DOIUrl":"https://doi.org/10.1109/LED.2025.3535601","url":null,"abstract":"In the development of the Schottky-type p-GaN gate HEMT, the instable <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> is always a highlighted problem. Under high <inline-formula> <tex-math>${V}_{text {DS}}$ </tex-math></inline-formula> bias, the potential of the floating p-GaN can be raised by the gate/drain coupled barrier lowering (GDCBL) effect, inducing a noticeable negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift. During the fast switching operation, the negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift severely aggravates the false turn-on problem. In this work, a split-p-GaN gate HEMT (SPG-HEMT) is demonstrated to effectively suppress the drain-induced negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift, enhancing the robustness against false turn-on. At <inline-formula> <tex-math>${V}_{text {DS}} =100$ </tex-math></inline-formula> V, the conventional p-GaN gate HEMT (Conv-HEMT) suffers a negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift of −0.33 V, while the SPG-HEMT exhibits only a minimal <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift of −0.07 V. In the SPG-HEMT, the GDCBL effect takes place only for the p-GaN near the drain side (p<inline-formula> <tex-math>$_{{2}}text {)}$ </tex-math></inline-formula>; the p-GaN near the source (p<inline-formula> <tex-math>$_{{1}}text {)}$ </tex-math></inline-formula> is isolated from p2 via the gate/p-GaN Schottky junctions, and the influence of drain bias upon p1 is shielded by p2. Then, the impact of negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift on false turn-on is evaluated by a half-bridge switching circuit. Due to the obvious negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift, the Conv-HEMT is falsely turned on when the <inline-formula> <tex-math>${V}_{text {GS}}$ </tex-math></inline-formula> ringing peak is still much lower than the static threshold voltage (<inline-formula> <tex-math>${V}_{{mathrm {th0}}})$ </tex-math></inline-formula>. In contrast, the SPG-HEMT starts to show false turn-on signal only when the <inline-formula> <tex-math>${V}_{text {GS}}$ </tex-math></inline-formula> ringing peak is near <inline-formula> <tex-math>${V}_{{mathrm {th0}}}$ </tex-math></inline-formula>. Overall, the unique device structure of the SPG-HEMT leads to a negligible negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift and enhances the robustness against false turn-on.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"628-631"},"PeriodicalIF":4.1,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Temperature Polycrystalline Silicon Thin-Film Transistor-Based Micro Light-Emitting Diode Pixel Circuit Using Quaternary Digital Pulse Width Modulation for Simple Structure and Short Delay Time","authors":"Hwarim Im;Eun Kyo Jung;Hye-Won Woo;Kook Chul Moon;Yong-Sang Kim","doi":"10.1109/LED.2025.3535586","DOIUrl":"https://doi.org/10.1109/LED.2025.3535586","url":null,"abstract":"We propose a low-temperature polycrystalline silicon thin-film transistor (TFT)-based micro light-emitting diode (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LED) pixel circuit using quaternary digital pulse width modulation (PWM). The proposed circuit uses a stepwise control signal to modulate the emission time of each subframe in four levels, thereby reducing the number of subframes by half compared with conventional binary digital driving. Because the stepwise control signal can directly change the PWM driving TFT from off-state to on-state, the proposed circuit exhibits a short delay time of <inline-formula> <tex-math>$1.83~mu $ </tex-math></inline-formula>s and low luminance variations of 3.45% without requiring a compensation structure for the threshold voltage of the PWM driving TFT. The proposed pixel circuit can be efficiently used in high-quality <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LED displays, ensuring a stable operation.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"608-611"},"PeriodicalIF":4.1,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Pixel Circuit With Improved Luminance Uniformity and Flicker for AMOLED Displays With a Wide VRR Range of 15 Hz to 360 Hz","authors":"Younsik Kim;Sung-Min Wee;Kyunghoon Chung;Byungchang Yu;Jaemyung Lim;Oh-Kyong Kwon","doi":"10.1109/LED.2025.3535717","DOIUrl":"https://doi.org/10.1109/LED.2025.3535717","url":null,"abstract":"This letter proposes a 6T2C pixel circuit designed for LTPS-based AMOLED displays to improve luminance uniformity and reduce flicker across a wide range of variable refresh rates (VRRs). The proposed circuit employs a two-step compensation method to address variations in the threshold voltage and subthreshold slope of driving thin-film transistors (TFTs), improving luminance uniformity. Additionally, it minimizes the hysteresis effect of TFTs using an inducing hole-trapping technique, resulting in lower flicker. The proposed pixel circuit was verified with 48 samples for a 5.8-inch QHD AMOLED display, achieving notable reductions in emission current errors (ECEs) within a VRR range of 15 Hz to 360 Hz. The luminance uniformity performance was improved compared to a previous 7T2C circuit, with measured spatial ECEs of +3.4/−3.4 LSB versus +4.1/−4.2 LSB at the 256th gray level. The flicker performance was also improved, with measured temporal ECEs of +0.4 LSB and −1.1 LSB versus −0.8 LSB and −3.2 LSB at the 16th and 256th gray levels, respectively.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"600-603"},"PeriodicalIF":4.1,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scalable Vertical In–Ga–As Nanowire MOSFET With 67 mV/dec at 126μm Gate Width","authors":"Anette Löfstrand;Marcus E. Sandberg;Johannes Svensson;Lars Fhager","doi":"10.1109/LED.2025.3535408","DOIUrl":"https://doi.org/10.1109/LED.2025.3535408","url":null,"abstract":"Heterogeneous integration of III-V narrow bandgap transistors on silicon technology is desirable for high frequency circuit implementations. Such high-speed transistors must, however, scale to large gate widths to be suitable for general circuit design. Averaging among many variable channels is a key challenge for nanowire devices. A simplified, but high-speed compatible, nanowire device process was developed here. It utilizes metal plugs to reduce complexity in the gate patterning step. It also implements a spin coated BCB low-k dielectric as top interlayer. A vertical In-Ga–As MOSFET with 1600 nanowire channels and 110 nm gate length achieved a minimum subthreshold swing of <inline-formula> <tex-math>$mathrm {67~mathrm{mV/dec} }$ </tex-math></inline-formula> at <inline-formula> <tex-math>$mathrm {126~mu text {m} }$ </tex-math></inline-formula> gate width. The maximum transconductance was <inline-formula> <tex-math>$mathrm {0.88~text {m}text {S} /mu text {m}}$ </tex-math></inline-formula> at 0.5 V drain-source voltage, with <inline-formula> <tex-math>$mathrm {0.22~text {m}text {A} /mu text {m}}$ </tex-math></inline-formula> normalized drain current. These long-channel results are on par with state-of-the art, but achieved for a device scaled to unprecedented device width. In tandem with the BCB interlayer, these results promise a back-end-of-line compatible high-speed vertical nanowire technology for integration on silicon.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"560-563"},"PeriodicalIF":4.1,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strain-Enhanced Responsivity of Scalable and Flexible Diamond UV Detector","authors":"Jixiang Jing;Yumeng Luo;Yicheng Wang;Zhongqiang Wang;Qi Wang;Kwai Hei Li;Zhiqin Chu","doi":"10.1109/LED.2025.3535477","DOIUrl":"https://doi.org/10.1109/LED.2025.3535477","url":null,"abstract":"In this letter, we present scalable and flexible diamond UV detectors. A 2-inch, 1-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick diamond film is exfoliated from its heteroepitaxial silicon substrate and transferred to a soft PDMS substrate, forming the foundation for the flexible detector. Measurement under strains of 0%, 0.6%, and 1.2% reveals a decrease in the bandgap of diamond film from 5.31 eV to 5.18 eV and 5.06 eV, respectively. This strain-induced narrowing of the bandgap improves the responsivity of diamond detectors under UV illumination. The elastic strain engineering on diamonds, being simple and effective, provides a new route to improve the performance of diamond UV detectors, promising to accelerate the development of next-generation flexible diamond electronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"541-544"},"PeriodicalIF":4.1,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Capacitive Crossbar Array for Solving Matrix Equations in One-Shot","authors":"Madhav Vadlamani;Jianwei Jia;Tian Xie;Yuan-Chun Luo;Junmo Lee;Shaolan Li;Shimeng Yu","doi":"10.1109/LED.2025.3533607","DOIUrl":"https://doi.org/10.1109/LED.2025.3533607","url":null,"abstract":"The resistive crossbar with a feedback loop has been proposed for solving matrix equations in a linear system with the current-domain computation. But the resistive approach suffers from high static power especially when the resistance is low. To overcome the challenges, we leverage C-V asymmetry in the ferroelectric capacitors of a crossbar array for the energy-efficient charge-domain computation. In this work, we demonstrate that such a capacitive crossbar when operated in negative feedback could solve the matrix problem <inline-formula> <tex-math>$Ax = {b}$ </tex-math></inline-formula> where x is the unknown vector. A comparative study shows a much lower power consumption (~1000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>) for such a matrix solver when compared to the resistive crossbar counterpart.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 3","pages":"389-392"},"PeriodicalIF":4.1,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}