Bit Line Hammering in Si-Based VCT DRAM: A New Security Challenge and Its Mitigation

Abstract

We introduce the Bit Line Hammer (BL hammer) effect, a serious disturbance mechanism in 4F2 DRAM with Si-based Vertical Channel Transistors (VCT). We demonstrate that a specifically designed BL attack pattern, featuring asymmetry and an appropriate toggling frequency, can trigger numerous bit-flips under JEDEC standards, especially at elevated temperatures. This uncovers an unexplored security vulnerability in VCT DRAM cells, with implications for data integrity in advanced memory technologies. Finally, we propose a mitigation strategy to improve cell’s resistance to the BL hammering.