IEEE Electron Device Letters最新文献

Intermittency and Persistence of Switching Modes in HfO2-Based Memristors 基于hfo2的忆阻器开关模式的间歇性和持久性

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-06 DOI: 10.1109/LED.2026.3719434

E. Miranda;A. Cantudo;F. Jiménez-Molinos;J. Suñé;M. B. González;J. B. Roldán

{"title":"Intermittency and Persistence of Switching Modes in HfO2-Based Memristors","authors":"E. Miranda;A. Cantudo;F. Jiménez-Molinos;J. Suñé;M. B. González;J. B. Roldán","doi":"10.1109/LED.2026.3719434","DOIUrl":"https://doi.org/10.1109/LED.2026.3719434","url":null,"abstract":"A distinct form of variability in HfO2-based memristive devices is experimentally identified and analyzed. Unlike conventional cycle-to-cycle (C2C) variability, which is commonly associated with fluctuations within a single switching mechanism, the observed behaviour originates from the intermittent coexistence of well-distinguishable conduction modes. The devices exhibit spontaneous transitions between bipolar resistive switching (BRS) and complementary resistive switching (CRS), giving rise to persistent conduction states interrupted by abrupt mode changes. Statistical analysis based on the Wald-Wolfowitz runs test reveals statistically significant temporal correlations, indicating that the switching dynamics cannot be described as a purely random process. The voltage ramp rate is found to strongly influence the relative occurrence of both modes, progressively suppressing the CRS response until only the BRS mode remains observable at sufficiently high ramp rates. Numerical simulations based on the dynamic memdiode model reproduce the experimentally observed mode-switching behaviour and attribute its origin to the partial reconfiguration of the conductive filament. These results establish intermittency and persistence as key descriptors of conduction-mode variability in resistive switching dielectrics, revealing a form of variability that extends beyond conventional C2C fluctuations.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2119-2122"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11644051","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Passivation Unlocks Enhanced Stability in BEOL-Compatible High-Voltage In2O3 Transistors for On-Chip Power Conversion 钝化解锁增强稳定性的beol兼容的高电压In2O3晶体管片上电源转换

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-12 DOI: 10.1109/LED.2026.3722899

Jennifer Toy;Taikyu Kim;Jeong-Kyu Kim;Christian Papachristodoulou;Jimin Kang;H.-S. Philip Wong;Srabanti Chowdhury

{"title":"Passivation Unlocks Enhanced Stability in BEOL-Compatible High-Voltage In2O3 Transistors for On-Chip Power Conversion","authors":"Jennifer Toy;Taikyu Kim;Jeong-Kyu Kim;Christian Papachristodoulou;Jimin Kang;H.-S. Philip Wong;Srabanti Chowdhury","doi":"10.1109/LED.2026.3722899","DOIUrl":"https://doi.org/10.1109/LED.2026.3722899","url":null,"abstract":"This study demonstrates high voltage (HV), back-end-of-line (BEOL)-compatible, top-gate In2O3 transistors designed for scalable on-chip power converters in monolithic-3D (M3D) systems. 8-nm-thick In2O3 transistors exhibit current modulation ratio (<inline-formula> <tex-math>${I}_{text {ON/ {OFF}}}text {)} gt 10^{{7}}$ </tex-math></inline-formula>, subthreshold swing (<italic>SS) <inline-formula> <tex-math>$approx 108$ </tex-math></inline-formula> mV/dec, on-resistance (<inline-formula> <tex-math>${R}_{text {ON}}text {)} approx 0.48 Omega cdot $ </tex-math></inline-formula>mm2, and breakdown voltage (<inline-formula> <tex-math>${V}_{text {BD}}text {)} approx 414$ </tex-math></inline-formula> V. While threshold voltage (<inline-formula> <tex-math>${V}_{text {TH}}text {)}$ </tex-math></inline-formula> remains stable under positive/negative bias temperature stress (PBTS/NBTS) even at <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C, the devices exhibit unconventional on-current (<inline-formula> <tex-math>${I}_{text {ON}}text {)}$ </tex-math></inline-formula> loss under NBTS and pronounced <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula> collapse under hot carrier stress. These <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula> degradations are greatly mitigated by passivating the access-region. This study reveals the dual-edged effect of the access region in HV oxide transistors in enabling high-voltage operation while triggering reliability penalties and establishes passivation as a practical route to mitigate <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula> degradation.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2059-2062"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11653284","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

All-GaN Monolithic 2T1C-μLED Pixel With MHz Optical Modulation for High-Refresh-Rate Microdisplays 用于高刷新率微显示器的全氮化镓单片2T1C μ led像素与MHz光调制

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-03 DOI: 10.1109/LED.2026.3718731

Ran Zhang;Hongping Liu;Yuefei Cai

{"title":"All-GaN Monolithic 2T1C-μLED Pixel With MHz Optical Modulation for High-Refresh-Rate Microdisplays","authors":"Ran Zhang;Hongping Liu;Yuefei Cai","doi":"10.1109/LED.2026.3718731","DOIUrl":"https://doi.org/10.1109/LED.2026.3718731","url":null,"abstract":"High-refresh-rate active-matrix microdisplays are essential components for many high-end applications, such as augmented reality (AR) displays. In this work, an all-GaN monolithic active micro-light-emitting diode (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LED) pixel with optical modulation up to 2 MHz is demonstrated. The pixel consists of one <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>m-diameter <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LED, two depletion-mode GaN high-electron-mobility transistors (HEMTs), and one metal-insulator-metal (MIM) storage capacitor (2T1C), with a total footprint of <inline-formula> <tex-math>$60~mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times 60~mu $ </tex-math></inline-formula>m. The GaN-based 2T1C-driven circuit is integrated monolithically with <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LEDs formed via selective-area growth (SAG) without sidewall etching. Static performance of the 2T1C-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LED circuit has been tested under different <inline-formula> <tex-math>${V}_{text {Data}}$ </tex-math></inline-formula> conditions. Transient measurements show its capability for “write-on, hold-on, write-off, and hold-off” operation, with both electrical and optical modulation up to 2 MHz, indicating great potential for high-end AR microdisplays.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"1987-1990"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Voltage (600 V) Dynamic Switching in Al0.6Ga0.4N-Channel HEMTs With Multiple Field-Plates 多场极板al0.6 ga0.4 n沟道hemt的高压（600 V）动态开关

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-21 DOI: 10.1109/LED.2026.3725547

Md Tahmidul Alam;Khush Gohel;Brahmani Challa;Shuwen Xie;Swarnav Mukhopadhyay;Guangying Wang;Surjava Sanyal;Ruixin Bai;Shubhra S. Pasayat;Chirag Gupta

{"title":"High-Voltage (600 V) Dynamic Switching in Al0.6Ga0.4N-Channel HEMTs With Multiple Field-Plates","authors":"Md Tahmidul Alam;Khush Gohel;Brahmani Challa;Shuwen Xie;Swarnav Mukhopadhyay;Guangying Wang;Surjava Sanyal;Ruixin Bai;Shubhra S. Pasayat;Chirag Gupta","doi":"10.1109/LED.2026.3725547","DOIUrl":"https://doi.org/10.1109/LED.2026.3725547","url":null,"abstract":"Al<inline-formula> <tex-math>${}_{{0}.{6}}$ </tex-math></inline-formula>Ga<inline-formula> <tex-math>${}_{{0}.{4}}$ </tex-math></inline-formula>N-channel HEMTs with Schottky gates, dual field plates, and SiO2 passivation were fabricated on sapphire substrate. For devices with a gate-to-drain spacing of <inline-formula> <tex-math>$5~mu $ </tex-math></inline-formula>m, the average on-resistance was <inline-formula> <tex-math>$20.3~Omega $ </tex-math></inline-formula>.mm (1.67 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>.cm<inline-formula> <tex-math>${}^{{2}}text {)}$ </tex-math></inline-formula>. A peak transconductance of 43 mS/mm and a maximum breakdown voltage of 1020 V were achieved, with low gate leakage current. Pulsed I-V measurements performed at V<inline-formula> <tex-math>${}_{textit {DS},{Q}}^{}=40$ </tex-math></inline-formula> V with a 100-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s pulse width showed no measurable current collapse. Under hard switching conditions, transient dynamic on-resistance (R<inline-formula> <tex-math>${}_{textit {ON},textit {DYN}}text {)}$ </tex-math></inline-formula> was then measured after 10-ms off-state stress at 40, 400, and 600 V. The lowest measured R<inline-formula> <tex-math>${}_{textit {ON},textit {DYN}}$ </tex-math></inline-formula> increases were 7%, 26%, and 31% after 40-, 400-, and 600-V stress, respectively, within <inline-formula> <tex-math>$200~mu $ </tex-math></inline-formula>s after switching. Under 1000-cycles of 400-V off-state stress, the dynamic on-resistance increase reached a maximum of 58% after approximately 450 cycles and then decreased to 52% after 1000 cycles. No permanent degradation in output current or gate leakage current was observed after 1000 stress cycles, indicating the promising high-voltage dynamic robustness of UWBG AlGaN-channel HEMTs for power switching applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"1999-2002"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Monolithic Integration of Hybrid 2T0C DRAM/FeRAM With In-Situ Weight Transfer 具有原位重量传递的混合2T0C DRAM/FeRAM的单片集成

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-07-31 DOI: 10.1109/LED.2026.3718712

Junchi Cheng;Quanyi Tu;Renhao Xue;Ruizhan Yan;Wenjuan Zhou;Mansun Chan;Xiwen Liu

{"title":"Monolithic Integration of Hybrid 2T0C DRAM/FeRAM With In-Situ Weight Transfer","authors":"Junchi Cheng;Quanyi Tu;Renhao Xue;Ruizhan Yan;Wenjuan Zhou;Mansun Chan;Xiwen Liu","doi":"10.1109/LED.2026.3718712","DOIUrl":"https://doi.org/10.1109/LED.2026.3718712","url":null,"abstract":"In this work, we demonstrate a monolithically integrated hybrid memory that stacks 2T0C DRAM on FeRAM and enables in-situ weight transfer within a single cell. Leveraging an MIS stack enabled by the monolithic all-ALD process, the 2T0C DRAM achieves an off-state leakage of <inline-formula> <tex-math>$8.48times 10^{-{14}}$ </tex-math></inline-formula> A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, retention >200 s, endurance <inline-formula> <tex-math>$gt 10^{{11}}$ </tex-math></inline-formula> cycles, and stress immunity >10000 s. Meanwhile, the all-ALD TiN/HZO/TiN FeRAM exhibits 2P<inline-formula> <tex-math>${}_{text {r}} gt 50~mu $ </tex-math></inline-formula>C/cm2, with projected retention >10 years and endurance <inline-formula> <tex-math>$gt 10^{{10}}$ </tex-math></inline-formula> cycles. Beyond co-integration, bidirectional in-situ transfer is realized without external circuits. Specifically, the large read window (high ION/I<inline-formula> <tex-math>${}_{text {OFF}}text {)}$ </tex-math></inline-formula> of the 2T0C DRAM programs its “0”/“1” states into distinct FeRAM polarization states via controlled polarization reversal, while the large displacement current during FeRAM switching is exploited to reload the FeRAM state back into the 2T0C DRAM. This hybrid cell enables in-cell bidirectional volatile–nonvolatile transfer, serving as a compact primitive for hybrid memory hierarchies, compute-in-memory, and energy-efficient AI with rapid updates and persistent storage.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2107-2110"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced 2Pr in 5-nm HZO Capacitors Under 300 °C RTP via Nb Electrode Engineering 通过Nb电极工程在300°C RTP下增强5nm HZO电容器的2Pr

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-03 DOI: 10.1109/LED.2026.3719105

Keyou Tong;Jing Xu;Xinyue Zhang;Wenjun Zhang;Weibing Liu;Shuai Yang;Xuanyi Li;Haisu Gao;Binbin Xu;Jiahan Yu;Wenjuan Xiong;Xiaoxue Ji;Jianhong Liu;Xiaolei Wang;Jun Luo

{"title":"Enhanced 2Pr in 5-nm HZO Capacitors Under 300 °C RTP via Nb Electrode Engineering","authors":"Keyou Tong;Jing Xu;Xinyue Zhang;Wenjun Zhang;Weibing Liu;Shuai Yang;Xuanyi Li;Haisu Gao;Binbin Xu;Jiahan Yu;Wenjuan Xiong;Xiaoxue Ji;Jianhong Liu;Xiaolei Wang;Jun Luo","doi":"10.1109/LED.2026.3719105","DOIUrl":"https://doi.org/10.1109/LED.2026.3719105","url":null,"abstract":"In this letter, Nb electrode engineering is proposed to enable low-temperature crystallization of ultrathin HZO, thereby extending its BEOL compatibility. Large <inline-formula> <tex-math>$2{P}_{text {r}}$ </tex-math></inline-formula> values of 53.6/<inline-formula> <tex-math>$56.4~mu $ </tex-math></inline-formula>C/cm2 at 3/3.5 MV/cm are achieved by the positive-up-negative-down (PUND) method in 5-nm HZO with Nb electrodes (NHN) after <inline-formula> <tex-math>$300~^{circ }$ </tex-math></inline-formula>C annealing, together with wake-up-free, negligible fatigue to 1E10 cycles (3 MV/cm, 100 kHz), and an extrapolated retention of 10 years at <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C. Specifically, the bottom Nb tends to form an Nb2O5 cap layer during the ALD process owing to its more negative oxide formation enthalpy, which suppresses oxygen scavenging and serves as an oxygen reservoir, thereby mitigating the redistribution and generation of interfacial oxygen vacancies (<inline-formula> <tex-math>${V}_{text {O}}text {)}$ </tex-math></inline-formula>. Meanwhile, the top Nb provides uniform nucleation sites due to the smaller Nb/HZO interfacial mismatch (~6%), promoting O-phase formation at ultra-low temperature. The synergy of above effects enables excellent ferroelectricity at a thermal budget as low as <inline-formula> <tex-math>$300~^{circ }$ </tex-math></inline-formula>C, which is of great interest for BEOL-compatible FeRAM applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2027-2030"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Achieving 0.82-dB NFmin in High-Drain-Bias GaN HEMTs via Buffer and Field-Plate Engineering for High-Linearity LNA Applications 通过缓冲和场极板工程实现高漏偏置GaN hemt中0.82 db NFmin的高线性LNA应用

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-06 DOI: 10.1109/LED.2026.3719413

Wenbo Ye;Ziyang Wang;Haowei Zhang;Haolan Qu;Xinbo Zou

{"title":"Achieving 0.82-dB NFmin in High-Drain-Bias GaN HEMTs via Buffer and Field-Plate Engineering for High-Linearity LNA Applications","authors":"Wenbo Ye;Ziyang Wang;Haowei Zhang;Haolan Qu;Xinbo Zou","doi":"10.1109/LED.2026.3719413","DOIUrl":"https://doi.org/10.1109/LED.2026.3719413","url":null,"abstract":"In this letter, minimum noise figure (<italic>NF<inline-formula> <tex-math>${}_{text{min} }$ </tex-math></inline-formula>) of GaN high-electron-mobility transistors (HEMTs) under high-drain bias (<inline-formula> <tex-math>$textit{V}_{text {DS}} gt text{20}$ </tex-math></inline-formula>V) is investigated and optimized for high-linearity low noise amplifier (LNA) applications. By employing a <inline-formula> <tex-math>$text{1}~mu $ </tex-math></inline-formula>m Fe-doped GaN buffer and a non-overlapping source field plate (SFP), the device achieves a <italic>NFmin of 0.82 dB at 3 GHz and a <inline-formula> <tex-math>$textit{V}_{text {DS}}$ </tex-math></inline-formula> of 24 V, while delivering an associated gain (<inline-formula> <tex-math>$textit{G}_{text {a}}$ </tex-math></inline-formula>) of 16.61 dB and an output third-order intercept point (OIP3) of 31.8 dBm. Experimental comparison and a physics-based noise model identify the sharp increase in gate leakage current (<inline-formula> <tex-math>$textit{I}_{text {G}}$ </tex-math></inline-formula>) as the dominant cause of <italic>NFmin degradation under high <inline-formula> <tex-math>$textit{V}_{text {DS}}$ </tex-math></inline-formula>, and confirm its suppression using <inline-formula> <tex-math>$text{1}~mu $ </tex-math></inline-formula>m Fe-doped buffer scheme. Moreover, a non-overlapping SFP suppresses the device’s thermal noise by lowering the intrinsic resistances (<inline-formula> <tex-math>$textit{R}_{text {i}}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$textit{R}_{text {gd}}$ </tex-math></inline-formula>). This work provides a novel design optimization strategy for high-bias, low-noise GaN HEMTs tailored for high-linearity LNA applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"1979-1982"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Normally-Off β-Ga2O3 Trench-Gate Current-Aperture Vertical Electron Transistors With High-Voltage Drain--Stress Stability 具有高压漏极应力稳定性的常关β-Ga2O3沟栅-电流-孔径垂直电子晶体管

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-02 DOI: 10.1109/LED.2026.3728000

Jiahao Yao;Hehe Gong;Gaofu Guo;Jiazhao Jia;Anjing Luo;Zineng Yang;Rongming Yin;Fang-Fang Ren;Shulin Gu;Xiaodong Zhang;Yuhao Zhang;Jiandong Ye

{"title":"Normally-Off β-Ga2O3 Trench-Gate Current-Aperture Vertical Electron Transistors With High-Voltage Drain--Stress Stability","authors":"Jiahao Yao;Hehe Gong;Gaofu Guo;Jiazhao Jia;Anjing Luo;Zineng Yang;Rongming Yin;Fang-Fang Ren;Shulin Gu;Xiaodong Zhang;Yuhao Zhang;Jiandong Ye","doi":"10.1109/LED.2026.3728000","DOIUrl":"https://doi.org/10.1109/LED.2026.3728000","url":null,"abstract":"Enhancement-mode (E-mode) <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 transistors are highly desired for kV-class power switching, but their realization remains challenging due to the lack of effective p-type doping. Fin- and trench-gate structures have been employed to achieve the E-mode operation, but they suffer gate-corner electric-field (E-field) crowding and thereby reliability concerns. Here we propose the deployment of the current aperture vertical electron transistor (CAVET) architecture to shield the trench-gate from high E-field. The fabricated trench-gate CAVET achieves a threshold voltage of 2.1 V, a small transfer hysteresis of 50 mV, a specific on-resistance of 13.4 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2, and a breakdown voltage of 1140 V. Its stability is investigated under high-bias drain stress, presenting small parametric shifts after 600 V stress for 1000 s. When elevating the stress bias to 1000 V, the device presents no gate failure, validating the effective E-field shielding. Notably, such high-bias stability tests have not been previously reported for Ga2O3 vertical transistors. Therefore, this work demonstrates a promising architecture for normally-off, kV-class <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 power transistors with high-voltage drain-stress stability.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2091-2094"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

PDA-Processed Hafnium-Based Capacitors With Ultrahigh-k (~81) Enabled by Capping Layers for Capacitive Memory Applications 采用封盖层实现超高k（~81）的pda加工铪基电容，用于电容存储应用

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-20 DOI: 10.1109/LED.2026.3725245

Xingcan Guo;Lei Wang;Kangli Xu;Chao Wu;Ruihong Yuan;Aolin Yuan;Hao Zhu;Qingqing Sun;David Wei Zhang;Jiajie Yu;Zhenhai Li;Lin Chen

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引用次数: 0

Comprehensive Variation Model of Hafnium-Based Ferroelectric Capacitors for High-Sigma Memory Window Simulation 用于高西格玛记忆窗口模拟的铪基铁电电容器综合变化模型

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-24 DOI: 10.1109/LED.2026.3726521

Diqing Su;Yannan Xu;Qingting Ding;Dongsen Chen;Shiqi Yue;Jianrui Cheng;Zhiwei Zheng;Hangbing Lv

引用次数: 0