IEEE Electron Device Letters最新文献

IEEE Transactions on Electron Devices Table of Contents IEEE电子器件汇刊目录

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-03-01 Epub Date: 2026-04-28 DOI: 10.1109/LED.2026.3682151

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IEEE Transactions on Electron Devices Table of Contents IEEE电子器件汇刊目录

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-02-26 DOI: 10.1109/LED.2026.3661316

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EDS Meetings Calendar EDS会议日程表

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-02-26 DOI: 10.1109/LED.2026.3661312

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IEEE Electron Device Letters Information for Authors IEEE电子器件通讯作者信息

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-02-26 DOI: 10.1109/LED.2026.3661314

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IEEE Transactions on Electron Devices Table of Contents IEEE电子器件汇刊目录

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-01-29 DOI: 10.1109/LED.2026.3652874

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IEEE Electron Device Letters Information for Authors IEEE电子器件通讯作者信息

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-01-29 DOI: 10.1109/LED.2026.3652870

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EDS Meetings Calendar EDS会议日程表

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-01-29 DOI: 10.1109/LED.2026.3652868

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Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications 《IEEE电子器件学报：用于射频、功率和光电子应用的超宽带隙半导体器件》特刊征文

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-01-29 DOI: 10.1109/LED.2026.3652872

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Impacts of EOT Scaling of ZrOx/HfOx Dielectric on Monolayer WSe2 Top-Gate p-MOSFETs ZrOx/HfOx介电介质EOT缩放对单层WSe2顶栅p- mosfet的影响

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-01-23 DOI: 10.1109/LED.2026.3657560

Yu-Wei Hsu;Yu-Tung Lin;Nien-En Chiang;Shao-Heng Chen;Ying-Zhan Chiu;Chen-Hsun Hsu;Ting-Hua Wei;Sin-Yue Lee;Zi-Quan Su;Hung-Li Chiang;I-Chih Ni;Tsung-En Lee;Chih-I Wu

{"title":"Impacts of EOT Scaling of ZrOx/HfOx Dielectric on Monolayer WSe2 Top-Gate p-MOSFETs","authors":"Yu-Wei Hsu;Yu-Tung Lin;Nien-En Chiang;Shao-Heng Chen;Ying-Zhan Chiu;Chen-Hsun Hsu;Ting-Hua Wei;Sin-Yue Lee;Zi-Quan Su;Hung-Li Chiang;I-Chih Ni;Tsung-En Lee;Chih-I Wu","doi":"10.1109/LED.2026.3657560","DOIUrl":"https://doi.org/10.1109/LED.2026.3657560","url":null,"abstract":"This work demonstrates the two-step elevated-temperature atomic layer deposit (ALD) process of bilayer ZrOx/HfOx relatively higher-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> dielectrics reported on chemical vapor deposit (CVD) monolayer (1L) WSe2 for top-gate dielectric. Top-gated 1L-WSe2 pFETs with a low subthreshold swing (S.S. ~60 mV/dec) are achieved at a low equivalent oxide thickness (EOT) of 0.8 nm. By scaling the physical thickness of this two-step bilayer ZrOx/HfOx dielectric with the pinhole-free AlOx nucleation layer down to 2 nm, the proposed gate stack exhibits a high effective dielectric constant (<inline-formula> <tex-math>$varepsilon _{text {eff}} sim 14$ </tex-math></inline-formula>) and strong reliability (breakdown field E<inline-formula> <tex-math>${}_{text {BD}} sim 21$ </tex-math></inline-formula> MV/cm) at the scaled EOT. This breakthrough in gate dielectric integration on p-type 1L-WSe2 enables balanced n/p performance for 2D-channel devices and enhances the feasibility of future low-power consumption CMOS applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 3","pages":"637-640"},"PeriodicalIF":4.5,"publicationDate":"2026-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147288171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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First Demonstration of High-Performance Three-Tier IGZO Channels Gate-All-Around Thin-Film Transistors With Novel Metal Interlayer Contact 具有新型金属层间接触的高性能三层IGZO通道栅全能薄膜晶体管的首次演示

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-01-19 DOI: 10.1109/LED.2026.3655893

Wen-Hsiang Lu;Yun-Hao Yeh;Chia-Tsong Chen;Wen-Hsin Chang;Tatsuro Maeda;Yao-Jen Lee;Yeong-Her Wang

{"title":"First Demonstration of High-Performance Three-Tier IGZO Channels Gate-All-Around Thin-Film Transistors With Novel Metal Interlayer Contact","authors":"Wen-Hsiang Lu;Yun-Hao Yeh;Chia-Tsong Chen;Wen-Hsin Chang;Tatsuro Maeda;Yao-Jen Lee;Yeong-Her Wang","doi":"10.1109/LED.2026.3655893","DOIUrl":"https://doi.org/10.1109/LED.2026.3655893","url":null,"abstract":"For the first time, highly integrated IGZO transistors suitable for back-end-of-line (BEOL) integration are demonstrated, leveraging an in-situ ozone interfacial layer (IL) treatment before HfO2 deposition. The ozone-treated gate-all-around (GAA) devices achieve an outstanding sub-threshold swing (S.S.) of 64 mV/dec at L = 150 nm, approaching the theoretical limit, and exhibit an Ion/Ioff ratio exceeding <inline-formula> <tex-math>${1}.{44}times {10} ^{{8}}$ </tex-math></inline-formula>. The ozone IL treatment significantly reduces oxygen vacancy (VO) concentration, enhancing channel integrity, electrostatic control, reliability, scalability, and subthreshold swing precision. This metal interlayer significantly reduces source/drain contact resistance, resulting in a <inline-formula> <tex-math>$2.3times $ </tex-math></inline-formula> performance enhancement for three-tier devices compared to single-tier counterparts. These combined advancements underscore the potential of IGZO GAA structures for next-generation high-performance semiconductor applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 3","pages":"621-624"},"PeriodicalIF":4.5,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147287853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0