Impacts of EOT Scaling of ZrOx/HfOx Dielectric on Monolayer WSe2 Top-Gate p-MOSFETs

This work demonstrates the two-step elevated-temperature atomic layer deposit (ALD) process of bilayer ZrO_x/HfO_x relatively higher- $\kappa $ dielectrics reported on chemical vapor deposit (CVD) monolayer (1L) WSe₂ for top-gate dielectric. Top-gated 1L-WSe₂ pFETs with a low subthreshold swing (S.S. ~60 mV/dec) are achieved at a low equivalent oxide thickness (EOT) of 0.8 nm. By scaling the physical thickness of this two-step bilayer ZrO_x/HfO_x dielectric with the pinhole-free AlO_x nucleation layer down to 2 nm, the proposed gate stack exhibits a high effective dielectric constant ( $\varepsilon _{\text {eff}} \sim 14$ ) and strong reliability (breakdown field E ${}_{\text {BD}} \sim 21$ MV/cm) at the scaled EOT. This breakthrough in gate dielectric integration on p-type 1L-WSe₂ enables balanced n/p performance for 2D-channel devices and enhances the feasibility of future low-power consumption CMOS applications.