IEEE Electron Device Letters最新文献

{"title":"Photolithographic PEDOT:PSS Electrodes for Transparent and Conformal Organic Transistors","authors":"Yanping Ni;Chuang Xue;Xiaoli Zhao;Peng Xue;Yanhong Tong;Qingxin Tang;Yichun Liu","doi":"10.1109/LED.2025.3540472","DOIUrl":"https://doi.org/10.1109/LED.2025.3540472","url":null,"abstract":"Poly(3,4-ethylenedioxythiophene):poly (styrenesulfonate) (PEDOT:PSS) is widely used as electrode material for transparent and conformal organic thin-film transistors (TC-OTFTs) owing to its excellent conductivity, high transparency, and good mechanical flexibility. However, due to the lack of high-precision and high-density transparent flexible electrodes, the high-level integration of TC-OTFTs faces a huge challenge. Here, we propose a simple protective layer photolithography strategy that successfully achieves non-destructive photolithography of PEDOT:PSS. The pattern feature size is down to 750 nm, which is the smallest size of PEDOT:PSS reported so far. Based on such high-precision transparent electrodes, we successfully fabricate TC-OTFTs with a device density up to 50,020 transistors <inline-formula> <tex-math>${text{cm}}^{-{2}}$ </tex-math></inline-formula>, which is the highest value reported for TC-OTFTs. More strikingly, the device showcases outstanding mobility of 1.51 cm2<inline-formula> <tex-math>${text{V}}^{-{1}} {text{s}}^{-{1}}$ </tex-math></inline-formula>. This work provides a reliable photolithography strategy to realize scalable fabrication and high-density integration of TC-OTFTs, offering a significant potential for developing wearable invisible electronics with high density and performance.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"604-607"},"PeriodicalIF":4.1,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Snapback-Free and Fast-Switching SOI LIGBT With Integrated Double Self-Biased MOSFET","authors":"Weizhong Chen;Xiangwei Zeng;Ao Wu;Cheng Li;Zhengsheng Han","doi":"10.1109/LED.2025.3539708","DOIUrl":"https://doi.org/10.1109/LED.2025.3539708","url":null,"abstract":"A novel SOI-LIGBT integrating a Double Self-driving MOSFET (DSM) is proposed. The DSM consists of a Self-Biased P-MOS (SBP) with a shorted main gate and a Self-Biased N-MOS (SBN) with a shorted auxiliary gate. These components are designed to function without additional gate signals, and they are driven automatically by the operating state of the LIGBT. During forward conduction, the SBP (<inline-formula> <tex-math>${V}_{text {GS,{P}}} gt {V}_{text {thp}}$ </tex-math></inline-formula>) is turned off, whereas the SBN gradually turns on as the <inline-formula> <tex-math>${V}_{text {CE}}$ </tex-math></inline-formula> increases. The P-buried substrate of SBN creates a potential barrier for electron carriers, effectively eliminating the snapback effect. During reverse conduction, the SBP (<inline-formula> <tex-math>${V}_{text {GS,{P}}} lt {V}_{text {thp}}$ </tex-math></inline-formula>) is turned on, and the SBN is turned off, functioning as a P-MOS in series with a PN-junction diode. During turn-off, the SBP (<inline-formula> <tex-math>${V}_{text {GS,{P}}} lt {V}_{text {thp}}$ </tex-math></inline-formula>) and the SBN (<inline-formula> <tex-math>${V}_{text {GS,{N}}} gt {V}_{text {thn}}$ </tex-math></inline-formula>) are reactivated to extract excess carriers. Consequently, the DSM-LIGBT achieves a superior tradeoff between <inline-formula> <tex-math>${V}_{text {ON}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${E}_{text {OFF}}$ </tex-math></inline-formula>. At <inline-formula> <tex-math>${V}_{text {ON}} =1.22$ </tex-math></inline-formula> V, the <inline-formula> <tex-math>${E}_{text {OFF}}$ </tex-math></inline-formula> is reduced by 30%, 30.32%, and 68.23% compared with SBM-LIGBT, TBSA-LIGBT, and SSA-LIGBT, respectively.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"537-540"},"PeriodicalIF":4.1,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced Capacitive Memory Window by Improving Remnant Polarization in Ferroelectric Capacitors for Non-Destructive Read","authors":"Shankha Mukherjee;Jasper Bizindavyi;Mihaela I. Popovici;Sergiu Clima;Yang Xiang;Gourab De;Attilio Belmonte;Gouri Sankar Kar;Francky Catthoor;Shimeng Yu;Valeri V. Afanas’Ev;Jan Van Houdt","doi":"10.1109/LED.2025.3539834","DOIUrl":"https://doi.org/10.1109/LED.2025.3539834","url":null,"abstract":"The unique concept of a non-volatile capacitive memory window (CMW) in ferroelectric (FE) capacitors (FeCAP) allows for a non-destructive read operation (NDRO). NDRO decouples the read- from the write-endurance which is ideal for random access memory and compute-in-memory applications. However, the optimal strategy to further improve the CMW remains uncertain. In this work, we first identify potential pathways to improve the CMW by studying the dependence of the relative dielectric permittivity (<inline-formula> <tex-math>$epsilon _{text {r}}$ </tex-math></inline-formula>) of a FE on the remnant polarization (<inline-formula> <tex-math>${P}_{text {R}}$ </tex-math></inline-formula>) and coercive field (<inline-formula> <tex-math>${E} _{text {C}}$ </tex-math></inline-formula>). Results show that a FE stack having a higher <inline-formula> <tex-math>${P}_{text {R}}$ </tex-math></inline-formula> and/or a lower <inline-formula> <tex-math>${E}_{text {C}}$ </tex-math></inline-formula> leads to an improved <inline-formula> <tex-math>$epsilon _{text {r}}$ </tex-math></inline-formula> and CMW for a given read-bias. Next, we experimentally demonstrate this and show that a trilayer FeCAP with an enhanced <inline-formula> <tex-math>$2{P}_{text {R}}$ </tex-math></inline-formula> achieves a high CMW<inline-formula> <tex-math>$_{epsilon }$ </tex-math></inline-formula> of ~20, which is ~1.5x higher than earlier best. Finally, we demonstrate a pulse-based NDRO confirming a robust 1.5x enhancement in CMW even after <inline-formula> <tex-math>$10^{{11}}$ </tex-math></inline-formula> NDRO cycles.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"576-579"},"PeriodicalIF":4.1,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High RF Performance AlGaN/GaN HEMTs on 6-in Si Substrate for Low Voltage Applications","authors":"Yuxi Zhou;Jiejie Zhu;Bowen Zhang;Qiyu Wang;Lingjie Qin;Lubing Wei;Mengdi Li;Binglu Chen;Mingchen Zhang;Yue Hao;Xiaohua Ma","doi":"10.1109/LED.2025.3539689","DOIUrl":"https://doi.org/10.1109/LED.2025.3539689","url":null,"abstract":"In this letter, AlGaN/GaN high electron mobility transistors (HEMTs) on a 6-inch Si substrate with excellent RF performance are presented for low voltage applications. Using regrown n+-InGaN ohmic contacts by metal-organic chemical vapor deposition, the ohmic contact resistance achieves an average value of <inline-formula> <tex-math>$0.08~Omega cdot $ </tex-math></inline-formula>mm on the whole wafer. With a gate length of 220 nm and a source-drain spacing of <inline-formula> <tex-math>$2.2~mu $ </tex-math></inline-formula>m, the device exhibits a saturation current of up to 1689 mA/mm and a peak transconductance of 436 mS/mm. Once the wafer was thinned to <inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>m, 3.6 GHz load-pull measurements for the HEMT with gate width (<inline-formula> <tex-math>${W}_{text {g}}text {)}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$2times 100~mu $ </tex-math></inline-formula>m at low drain voltages (<inline-formula> <tex-math>${V}_{text {d}}text {)}$ </tex-math></inline-formula> of 5-15 V indicate that the device exhibits maximum output power densities (<inline-formula> <tex-math>${P}_{ {text {out}, {max}}} )$ </tex-math></inline-formula> of 0.86-4.35 W/mm and peak power added efficiencies (PAE) of 63.96%-66.23%, which are the highest output power density and PAE from AlGaN/GaN HEMTs at the same operating voltage level in sub-6GHz. Furthermore, the HEMT with <inline-formula> <tex-math>${W}_{text {g}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$8times 125~mu $ </tex-math></inline-formula>m also shows high PAE of 60.4%/61.19% and <inline-formula> <tex-math>${P}_{ {text {out}, {max}}}$ </tex-math></inline-formula> of 0.56/0.75 W/mm at <inline-formula> <tex-math>${V}_{text {d}} =5$ </tex-math></inline-formula>/6 V. The excellent properties of these AlGaN/GaN HEMTs on Si illustrate their suitability for addressing specific RF application scenarios, including portable communication devices, wireless sensor networks and so on.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"549-552"},"PeriodicalIF":4.1,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of the P-Electrode Area Ratio on the Performance of Micro Light-Emitting Diodes for Display and Communication","authors":"Shi-Biao Liu;Ming-He Wan;Wen-An Guo;You-Cai Deng;Guo-Long Chen;Mai-Jia Lin;Hao-Chung Kuo;Yi-Jun Lu;You-Qin Lin;Zhong Chen;Ting-Zhu Wu","doi":"10.1109/LED.2025.3539655","DOIUrl":"https://doi.org/10.1109/LED.2025.3539655","url":null,"abstract":"In this letter, green micro-LEDs with a chip size of <inline-formula> <tex-math>$27 ; mu $ </tex-math></inline-formula>m and different P-electrode area ratios (20%, 30%, 40%, and 50%) were fabricated and characterized to determine the optimal P-electrode area ratio for display and communication. The results showed that increasing the P-electrode area ratio improved the uniformity in the current distribution of the micro-LED. However, it can also cause significant metal light-blocking. The optimal P-electrode area ratio of the micro-LED for displays was 30%, yielding optimal external quantum efficiency (EQE) and light output power (LOP). The optimal P-electrode area ratio of the micro-LED for communication was 50%, resulting in a marked improvement in the normalized frequency response and -3 dB bandwidth. It is crucial to select the appropriate P-electrode area ratio for the micro-LED depending on the applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"612-615"},"PeriodicalIF":4.1,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Flexible Low Dropout Regulator Based on InSnO Thin-Film Transistors With Superior Bending Robustness and Ultra-Low Quiescent Current","authors":"Tingrui Huang;Zuoxu Yu;Yuzhen Zhang;Di Gui;Mingming Liu;Kaizhi Sui;Wenting Xu;Guangan Yang;Wangran Wu;Weifeng Sun","doi":"10.1109/LED.2025.3539285","DOIUrl":"https://doi.org/10.1109/LED.2025.3539285","url":null,"abstract":"In this work, a flexible low dropout regulator (LDO) based on InSnO (ITO) thin film transistors (TFTs) on a 50-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m polyimide (PI) substrate is demonstrated for the first time. The LDO is realized through integrated depleted- and enhanced-mode (D-mode and E-mode) ITO TFTs with 6-nm and 4-nm thick ITO channel layers respectively. Low-current design in 4-transistors (4T) voltage reference and restriction of tail current in error amplifier are adopted to achieve ultra-low quiescent current (I<inline-formula> <tex-math>$_{text {q}}text {)}$ </tex-math></inline-formula> down to 10 nA for the LDO. The ITO TFTs show great electrical robustness in bending experiment under bent radii (r<inline-formula> <tex-math>$_{text {bent}}text {)}$ </tex-math></inline-formula> of 5 mm with threshold voltage shift (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<inline-formula> <tex-math>$_{text {th}}text {)}$ </tex-math></inline-formula> less than 0.01 V. Both the output voltage and line regulation of the LDO change little under rbent of 5 mm. Besides, after 10000 bending cycles, the electrical properties of ITO TFTs maintain unchanged. Therefore, the LDO exhibits great potential in flexible application of power management unit (PMU) with low power consumption.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"592-595"},"PeriodicalIF":4.1,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Charge Balance Design of 1200-V E-Mode p-GaN Gate HEMT Toward Enhanced Breakdown Voltage and Dynamic Stability","authors":"Junjie Yang;Jingjing Yu;Jiawei Cui;Sihang Liu;Teng Li;Yunhong Lao;Hao Chang;Maojun Wang;Jinyan Wang;Xiaosen Liu;Jin Wei;Bo Shen","doi":"10.1109/LED.2025.3539353","DOIUrl":"https://doi.org/10.1109/LED.2025.3539353","url":null,"abstract":"This work investigates the charge balance design of the 1200-V E-mode lateral superjunction p-GaN gate HEMT (SJ-HEMT) on sapphire substrate. The charge balance is formed through the alternative p-/n-pillars; the p-pillars are thinned p-GaN stripes, and the n-pillars are 2DEG stripes. The charge balance design on the static and dynamic performance of the SJ-HEMT was investigated by tuning the width of p-/n-pillars. The SJ-HEMT with charge balance yields a BV of 2655 V and a high BV/<inline-formula> <tex-math>${L}_{text {GD}}$ </tex-math></inline-formula> ratio of 1.56 MV/cm. Notably, the SJ-HEMT demonstrates effective suppression of trapping effects, which exhibits a strong correlation with the gap between two p-pillars. At charge balance design, the SJ-HEMT presents an excellent dynamic <inline-formula> <tex-math>${R}_{text {ON}}$ </tex-math></inline-formula>/static <inline-formula> <tex-math>${R}_{text {ON}}$ </tex-math></inline-formula> ratio of 1.28 under <inline-formula> <tex-math>${V}_{text {DS}}$ </tex-math></inline-formula> stress up to 1200 V. Our study also indicates a scaling of p-/n-pillars can further improve the dynamic <inline-formula> <tex-math>${R}_{text {ON}}$ </tex-math></inline-formula> performance. This work underscores the merits of charge-balanced design for high-performance 1200-V E-mode GaN power transistors.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"636-639"},"PeriodicalIF":4.1,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extremely Low Switching Current STT-MRAM Device With Double Spin Transfer Torque","authors":"Sinan Zou;Xing Zhao;Yuan Xue;Jianfeng Gao;Yan Cui;Jun Luo","doi":"10.1109/LED.2025.3539311","DOIUrl":"https://doi.org/10.1109/LED.2025.3539311","url":null,"abstract":"In this work, we demonstrate an STT-MRAM device with double reference layer that shows extremely low critical switching current density. A synthetic antiferromagnetic (SAF) layer [Co/Pt]n/Ru/[Co/Pt]m is used as the upper reference layer in the STT-MTJ device with perpendicular magnetic anisotropy (PMA) which can apply extra spin transfer torque to the free layer in the process of data writing. The ac R-I experimental results show that when the magnetization directions of upper and nether reference layer are antiparallel state, the JC is only 1.230 MA/cm2 for AP2P and 1.867 MA/cm2 for P2AP, when the pulse width is 10ns, which is more than <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> lower than the classical single reference layer STT-MTJ device with the close thermal stability. Our work provides a new way to achieve the ultra-low power STT-MRAM for IoT application.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"584-587"},"PeriodicalIF":4.1,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Approach to High-Performance Indium Gallium Zinc Oxide Transistors by Thermal Atomic Layer Deposition","authors":"Xingwei Ding;Luoqiang Wang;Kun Bai;Jun Yang;Jianhua Zhang","doi":"10.1109/LED.2025.3539304","DOIUrl":"https://doi.org/10.1109/LED.2025.3539304","url":null,"abstract":"Amorphous indium gallium zinc oxide (a-IGZO) thin films have been investigated to meet the high-resolution demands of augmented reality (AR) and virtual reality (VR) applications. In this study, we report on thin-film transistors (TFTs) derived from fully thermal atomic layer deposition (ALD), using IGZO as the channel layer and Al2O3 as the gate dielectric. By optimizing the deposition sequence and post-treatment processes, we achieved a high field-effect mobility of 52.5 cm2/Vs and a steep subthreshold swing of 116 mV/decade. This exceptional performance is attributed to the elevated In2O3 content in the IGZO thin films, which induces a substantial increase in sub-gap states adjacent to the conduction band minimum (CBM) and valence band maximum (VBM) while concurrently reducing the bandgap. At an elevated measurement temperature of 125 °C, the device exhibited an enhanced field-effect mobility of 60.4 cm2/Vs. These findings offer a new approach for optimizing metal oxide-based electronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"588-591"},"PeriodicalIF":4.1,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-Powered Photodetectors Based on PdSe2/ Al2O3/AlGaN Schottky Heterojunctions for Solar-Blind Ultraviolet Communication","authors":"Tingting Lin;Liwei Liu;Changjian Zhou;Wenliang Wang","doi":"10.1109/LED.2025.3539235","DOIUrl":"https://doi.org/10.1109/LED.2025.3539235","url":null,"abstract":"Generally, the slow response occurs in the AlGaN-based self-powered solar-blind photodetectors (SBPDs), owing to the low carrier mobility and high density of surface traps in AlGaN. To tackle the issues, PdSe2/Al2O3/AlGaN SBPDs have been proposed. Thanks to the direct growth of single-crystal PdSe2 with high work function and excellent mobility for constructing high-quality Schottky heterojunctions with a sharp interface and thin high-k Al2O3 interlayer for passivating dangling bonds at the interface and enhancing the Schottky barrier height, the as-prepared self-powered SBPDs demonstrate a fast response speed of 2.9/3.5 ms, a high responsivity of 95.3 mA/W, and an exceedingly good detectivity of <inline-formula> <tex-math>${1}.{41}times {10} ^{{12}}$ </tex-math></inline-formula> Jones @ 0 V under 254 nm light irradiation. Moreover, a solar-blind light communication (SBLC) system based on the device has been proposed. This work provides an effective approach for fabricating self-powered SBPDs towards application in the SBLC system.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"616-619"},"PeriodicalIF":4.1,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}