IEEE Electron Device Letters最新文献_第10页

First Demonstration of ε-Ga₂O₃/α-Ga₂O₃ HFET With a Sn-Doped Channel 带sn掺杂通道的ε-Ga₂O₃/α-Ga₂O₃HFET的首次证明

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-27 DOI: 10.1109/LED.2025.3584033

Han-Yin Liu;Ko-Fan Hu;Nei-En Chiu;Chun-Chien Lo;Zhong-Cheng Shen

{"title":"First Demonstration of ε-Ga₂O₃/α-Ga₂O₃ HFET With a Sn-Doped Channel","authors":"Han-Yin Liu;Ko-Fan Hu;Nei-En Chiu;Chun-Chien Lo;Zhong-Cheng Shen","doi":"10.1109/LED.2025.3584033","DOIUrl":"https://doi.org/10.1109/LED.2025.3584033","url":null,"abstract":"This study presents the <inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>-Ga2O3/<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-Ga2O3 heterostructure field-effect transistor (HFET) with a Sn-doped channel on a c-plane sapphire substrate using mist-CVD for the first time. <inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>-Ga2O3forms on the Sn-doped layer only when a c-plane sapphire substrate is used, a phenomenon absent from r-plane sapphire substrates. Secondary ion mass spectroscopy (SIMS) reveals that the Sn-doped layer in <inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>-Ga2O3/<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-Ga2O3 exhibits a smaller Sn diffusion range compared to <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-Ga2O3 homojunction, yet achieves lower sheet resistance, which may be attributed to a potential polarization effect in <inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>-Ga2O3/<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-Ga2O3 heterojunction. The <inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>-Ga2O3/<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-Ga2O3 HFET demonstrates superior performance, including a breakdown voltage of 1725 V, a specific on-resistance of 49.2 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2, and a power figure-of-merit of 60.48 MW/cm2, indicating its strong potential for power electronics applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1493-1496"},"PeriodicalIF":4.5,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bayesian Design of Metasurface Routers for CMOS Image Sensors via MetaRGBX-Net 基于MetaRGBX-Net的CMOS图像传感器超表面路由器的贝叶斯设计

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-27 DOI: 10.1109/LED.2025.3584027

JangHyeon Lee;ByoungGyu Kim;Yongkeun Lee

引用次数: 0

Top Spin-Orbit-Torque Switching of Magnetic Tunnel Junction With In-Situ Efficiency Quantification 磁隧道结顶部自旋-轨道-转矩开关的原位效率量化

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-26 DOI: 10.1109/LED.2025.3582335

Yan Huang;Kun Zhang;Chen Xiao;Qing Yang;Shijie Xu;Wenlong Cai;Daoqian Zhu;Jiakai Yang;Weisheng Zhao

{"title":"Top Spin-Orbit-Torque Switching of Magnetic Tunnel Junction With In-Situ Efficiency Quantification","authors":"Yan Huang;Kun Zhang;Chen Xiao;Qing Yang;Shijie Xu;Wenlong Cai;Daoqian Zhu;Jiakai Yang;Weisheng Zhao","doi":"10.1109/LED.2025.3582335","DOIUrl":"https://doi.org/10.1109/LED.2025.3582335","url":null,"abstract":"Spin orbit torque (SOT) magnetic random access memory (MRAM) has been regarded as a promising solution to overcome the ‘memory wall’ problem and led the way to better computing. However, conventional top-pinned SOT-MRAMs with perpendicular magnetic anisotropy (PMA) always suffer from the sidewall redeposition and over-etching problem during fabrications, as well as lower tunneling magnetoresistance than the bottom-pinned one. To address these problems, we reported a novel SOT-MRAM with PMA and bottom-pinned magnetic reference layer, realizing SOT switching by current flowing through top SOT channel with assistance of in-plane magnetic field. Such device, known as top-SOT PMA-magnetic tunnel junction (pMTJ), presents critical switching current density around 40 MA/cm2 at <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>s pulse width. In addition, we characterized the SOT efficiency directly in MRAM device and post-deposited top Pt electrode in top-SOT-pMTJ is demonstrated to be effective SOT source, inspiring flexible design of top-SOT-pMTJ stacks and fabrication process. The proposed structure with back-end-of-line compatible fabrication is anticipated to the mass production of high-performance SOT-MRAMs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1409-1412"},"PeriodicalIF":4.1,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2T1M and Complementary 3T2M Type-XY SOT-MRAM With High Performance and High Density 2T1M和互补的3T2M型xy型SOT-MRAM，高性能高密度

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-24 DOI: 10.1109/LED.2025.3582797

C.-Y Hu;M. Y. Song;G. L. Chen;K. M. Chen;K. T. Chang;I. J. Wang;Y. C. Hsin;S. Y. Yang;S. H. Li;J. H. Wei;T. Y. Lee;X. Y. Bao

引用次数: 0

GaN Bootstrapping Amplifier IC Operating at up to 800 °C Temperature GaN自举放大器IC工作温度高达800°C

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-24 DOI: 10.1109/LED.2025.3582714

Yixin Xiong;Ajay K. Visvkarma;Rian Guan;Nathan S. Banner;Chan-Wen Chiu;Xiaojun Zheng;Suzanne E. Mohney;Thomas N. Jackson;Rongming Chu

{"title":"GaN Bootstrapping Amplifier IC Operating at up to 800 °C Temperature","authors":"Yixin Xiong;Ajay K. Visvkarma;Rian Guan;Nathan S. Banner;Chan-Wen Chiu;Xiaojun Zheng;Suzanne E. Mohney;Thomas N. Jackson;Rongming Chu","doi":"10.1109/LED.2025.3582714","DOIUrl":"https://doi.org/10.1109/LED.2025.3582714","url":null,"abstract":"A gallium nitride bootstrapping amplifier integrated circuit is demonstrated for high-temperature applications. The amplifier leverages bootstrapping gain-boosting technology and incorporates five monolithically integrated depletion-mode gallium nitride high electron mobility transistors, enabling an operation temperature up to 800°C in N2 environment. Those transistors feature a threshold voltage of approximately −2 V. Under a gate-to-source voltage of 5 V, the on-state current density decreased from 167 mA/mm at 25°C to 45 mA/mm at 800°C. At 25°C, the amplifier exhibits a DC gain of 26.3 dB with a unity gain frequency of 8.9 MHz. At 800°C, the amplifier delivers a DC gain of 31 dB and a unity gain frequency of 1.4 MHz. In addition, no significant degradation was observed after holding the transistor and amplifier unbiased for an hour at 800°C. This amplifier integrated circuit demonstrates the competitiveness of gallium nitride high electron mobility transistors as a promising technology for high-temperature electronics, up to 800°C.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1309-1312"},"PeriodicalIF":4.1,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144704965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Top-Gate Atomic-Layer-Deposited Oxide Semiconductor Transistors With Large Memory Window and Non-Ferroelectric HfO₂ Gate Stack 具有大存储窗口和非铁电HfO 2栅极堆叠的顶栅原子层沉积氧化物半导体晶体管

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-23 DOI: 10.1109/LED.2025.3581599

Kai Jiang;Ziheng Wang;Zhiyu Lin;Zhenyu Chen;Jinxiu Zhao;Liankai Zheng;Chen Wang;Siying Li;Shan-Ting Zhang;Dongdong Li;Xiuyan Li;Xiaojun Guo;Mengwei Si

引用次数: 0

Resistance-Tuned Electrode Strategy for Achieving an Ultra-Wide Linear Range in Iontronic Pressure Sensors 在离子压力传感器中实现超宽线性范围的电阻调谐电极策略

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-23 DOI: 10.1109/LED.2025.3581987

Hua Xue;Ye Teng;Jiahe Li;Liyu Hu;Yuxuan Ding;Xu Chen;Haoxi Wang;Fan Li;Hongran Zhao;Xiuzhu Lin;Tong Zhang

引用次数: 0

Manufacturing-Friendly SOT-MTJ Device With High Reliability and Switching Efficiency 具有高可靠性和开关效率的制造友好型SOT-MTJ器件

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-23 DOI: 10.1109/LED.2025.3581997

Lei Zhao;Shasha Wang;Hengan Zhou;Xingyu Zhu;Kaiyuan Zhou;Zhenghui Ji;Guilin Chen;Yang Gao;Enlong Liu;Wenlong Yang;Difei Yuan;Ming Wang;Zejie Zheng;Xiaolei Yang;Shikun He

{"title":"Manufacturing-Friendly SOT-MTJ Device With High Reliability and Switching Efficiency","authors":"Lei Zhao;Shasha Wang;Hengan Zhou;Xingyu Zhu;Kaiyuan Zhou;Zhenghui Ji;Guilin Chen;Yang Gao;Enlong Liu;Wenlong Yang;Difei Yuan;Ming Wang;Zejie Zheng;Xiaolei Yang;Shikun He","doi":"10.1109/LED.2025.3581997","DOIUrl":"https://doi.org/10.1109/LED.2025.3581997","url":null,"abstract":"We propose a novel manufacturing-friendly self-aligned rounded-rectangle (SARR) spin-orbit torque magnetic tunnel junction (SOT-MTJ) device, in which the rounded-rectangle-shaped MTJ pillar and SOT channel are defined by single-step etch process. Two via-type bottom electrodes (BEs) are located at both ends beneath the MTJ pillar, with their entire top surfaces covered by the MTJ pillar. This device architecture eliminates the need for precise etch-stop control and can fundamentally address the critical process window limitation that has plagued the conventional SOT-MTJ fabrication. In addition, the tunneling magnetoresistance (TMR) of as high as 125%, reliable electrical switching down to 2 ns and over <inline-formula> <tex-math>$10^{{12}}$ </tex-math></inline-formula> writing cycles are achieved in the device. The SARR SOT-MTJ with perpendicular magnetic anisotropy (PMA) exhibits a significant enhancement in thermal stability (<inline-formula> <tex-math>$Delta text {)}$ </tex-math></inline-formula> while achieving approximately 1.5X switching efficiency (<inline-formula> <tex-math>${Delta /}{I}_{{c}{0}}text {)}$ </tex-math></inline-formula> improvement when its short side matches the diameter of the conventional circular SOT-MTJ with PMA. We conclude that the proposed SARR SOT-MTJ device, featuring excellent performance, shows great potential in the development of large-scale SOT-MRAM chip.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1345-1348"},"PeriodicalIF":4.1,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Capacitorless Neuron With Volatile Analog Pt/C/NbOx/TiN Memristor 具有挥发性模拟Pt/C/NbOx/TiN忆阻器的无电容神经元

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-20 DOI: 10.1109/LED.2025.3581554

Wenbin Guo;Hong Huang;Zhe Feng;Jianxun Zou;Zhihao Lin;Zuyu Xu;Yunlai Zhu;Yuehua Dai;Zuheng Wu

{"title":"A Capacitorless Neuron With Volatile Analog Pt/C/NbOx/TiN Memristor","authors":"Wenbin Guo;Hong Huang;Zhe Feng;Jianxun Zou;Zhihao Lin;Zuyu Xu;Yunlai Zhu;Yuehua Dai;Zuheng Wu","doi":"10.1109/LED.2025.3581554","DOIUrl":"https://doi.org/10.1109/LED.2025.3581554","url":null,"abstract":"Artificial neurons, as key components for implementing spiking neural networks (SNNs), are essential for neuromorphic systems to achieve efficient decision-making. Yet, conventional implementations require bulky capacitors or reset circuits that limit integration density and reliability. In this work, a capacitorless artificial neuron based on volatile analogue Pt/C/NbO<inline-formula> <tex-math>${}_{boldsymbol {x}}$ </tex-math></inline-formula>/TiN memristor is demonstrated, featuring highly uniform characteristics, excellent linear response, and fast relaxation process. The device inherently enables basic integration and leakage functions without additional capacitors. The neuron parameters can be flexibly adjusted by finely modulating input pulses to support different application scenarios. Furthermore, we constructed a two-layer SNN using time-to-first-spike (TTFS) coding, achieving about 98.9% accuracy on the MNIST dataset while reducing the average spike count by 93.8% compared to rate coding. The proposed scheme demonstrates great potential for achieving efficient and flexible neuromorphic systems.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1425-1428"},"PeriodicalIF":4.1,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bottom Charge-Modulated Field Limiting Rings Termination With N-P-N Sandwich Epitaxial Wafers for 4H-SiC Devices 用于4H-SiC器件的N-P-N夹层外延片底电荷调制场限制环端接

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-20 DOI: 10.1109/LED.2025.3581587

Jun Yuan;Zhijie Cheng;Fei Guo;Kuan Wang;Wei Chen;Yangyang Wu;Shaodong Xu;Rong Zhang;Guoqing Xin;Zhiqiang Wang

{"title":"A Bottom Charge-Modulated Field Limiting Rings Termination With N-P-N Sandwich Epitaxial Wafers for 4H-SiC Devices","authors":"Jun Yuan;Zhijie Cheng;Fei Guo;Kuan Wang;Wei Chen;Yangyang Wu;Shaodong Xu;Rong Zhang;Guoqing Xin;Zhiqiang Wang","doi":"10.1109/LED.2025.3581587","DOIUrl":"https://doi.org/10.1109/LED.2025.3581587","url":null,"abstract":"In this letter, a bottom charge-modulated field limiting rings termination with N-P-N sandwich epitaxial wafers for 4H-SiC devices is proposed and experimentally demonstrated. The proposed termination has more stable breakdown voltage than the conventional structure, because the lower concentration of P+ buried layer can be completely depleted. The breakdown voltage is as high as 1730 V. With the increase of temperature, the breakdown voltage continues to rise and has a relatively stable temperature coefficient. Further, the influence of N+ current spread layer on the breakdown ability of different epitaxial designs is fully discussed, and the reasonable electric field distribution of the proposed termination is demonstrated. It is found that high P+ buried layer concentration will lead to uneven distribution of electric field. However, the P+ buried layer has sufficient design margin. It is verified that the proposed termination has less influence on over etching depth in the P-shield region and initial ring spacing. The proposed termination has excellent breakdown performance, indicating the potential for power devices of the future.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1297-1300"},"PeriodicalIF":4.1,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0