IEEE Electron Device Letters最新文献_第9页

6773 PPI GaN-Based Blue Micro-LED Displays Fabricated by Monolithic Integration Technology 基于单片集成技术的6773 PPI gan蓝色微型led显示屏

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584085

Yongzhou Zhao;Qi Wang;Zheng Qin;Feifan Ma;Haihui Xin;Kaiyi Wu;Xiuheng Zhou;Guangchao Dai;Liangyu Xu;Xin Zheng;Tian Tang;Xiaofeng Chen;Likai Xun;Yongxing Liu;Liang Tian;Yi Huang;Hongsheng Zhang

引用次数: 0

Cryogenic Ferroelectric Behavior of Wurtzite Ferroelectrics 纤锌矿铁电体的低温铁电行为

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584071

Ruiqing Wang;Jiuren Zhou;Siying Zheng;Feng Zhu;Wenxin Sun;Haiwen Xu;Bochang Li;Yan Liu;Yue Hao;Genquan Han

引用次数: 0

Novel Silica Waveguide-Type Polarization Beam Splitters Based on MMI Coupler With Extraordinary Gratings 基于特殊光栅MMI耦合器的新型硅波导偏振分束器

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584262

Manzhuo Wang;Xinchao Zhang;Yu Xin;Tingyu Liu;Jimin Fang;Xiaoqiang Sun;Yuanda Wu;Daming Zhang

引用次数: 0

Novel Quasi-Unipolar MOS Pinch-Off Device With Zero-Biased BJT and Its Experiments 新型零偏BJT准单极MOS掐断器件及其实验

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584042

Teng Liu;Wentong Zhang;Qiyi Wu;Guoliang Yao;Lihui Gu;Nailong He;Sen Zhang;Shixiong Chong;Yuheng Yao;Yongyu Shi;Ming Qiao;Zhaoji Li;Bo Zhang

{"title":"Novel Quasi-Unipolar MOS Pinch-Off Device With Zero-Biased BJT and Its Experiments","authors":"Teng Liu;Wentong Zhang;Qiyi Wu;Guoliang Yao;Lihui Gu;Nailong He;Sen Zhang;Shixiong Chong;Yuheng Yao;Yongyu Shi;Ming Qiao;Zhaoji Li;Bo Zhang","doi":"10.1109/LED.2025.3584042","DOIUrl":"https://doi.org/10.1109/LED.2025.3584042","url":null,"abstract":"A novel quasi-unipolar MOS pinch-off device (MPD) is proposed and experimentally demonstrated in this letter. The MPD integrates a collector-junction zero-biased bipolar junction transistor (z-BJT) and a MOS pinch-off structure. The MOS pinch-off mechanism alleviates the inherent trade-off in conventional JFET where the necessity to sacrifice current capability to reduce the pinch-off voltage <inline-formula> <tex-math>${V}_{text {off}}$ </tex-math></inline-formula>, and a 70% increase in current at the same <inline-formula> <tex-math>${V}_{text {off}}$ </tex-math></inline-formula> is facilitated. The z-BJT eliminates hole injection into the P-sub, enabling the MPD to operate in a unipolar mode except for the base region of the BJT. This quasi-unipolar mode leads to a reduced P-sub leakage current by more than 3 orders of magnitude compared to that of conventional high-voltage diode. The MPD has been fabricated on a high voltage Bipolar-CMOS-DMOS (BCD) process platform. Experiments demonstrated that the MPD exhibits a breakdown voltage <inline-formula> <tex-math>${V}_{text {B}}$ </tex-math></inline-formula> of 832 V, a <inline-formula> <tex-math>${V}_{text {off}}$ </tex-math></inline-formula> of 20 V, an on-state current exceeding 40 mA, and an off-state substrate leakage current of less than 10 nA. This device has successfully entered large-scale mass production.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1581-1584"},"PeriodicalIF":4.5,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of Electromagnetic and Thermal Performance of MEMS Inductor Based on Microcoil Array Strategy 基于微线圈阵列策略的MEMS电感器电磁与热性能分析

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584108

Cheng Yi;Hongyu Chen;Xiang Qiu;Xiaolong Chen;Haochen Wu;Xinxing Xia;Xuecheng Sun

引用次数: 0

Anomalous Decrease of Field-Emission Tunneling Current for Poly-Si/4H-SiC Power Heterojunction Under Reverse Bias Stress 反向偏置应力下多晶硅/4H-SiC功率异质结场发射隧穿电流的异常减小

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584419

Hao Fu;Zilong Wu;Xiangrui Fan;Xinyu Zhang;Haozhu Pei;Zhaoxiang Wei;Junhou Cao;Xudong Zhu;Jiaxing Wei;Siyang Liu;Weifeng Sun

{"title":"Anomalous Decrease of Field-Emission Tunneling Current for Poly-Si/4H-SiC Power Heterojunction Under Reverse Bias Stress","authors":"Hao Fu;Zilong Wu;Xiangrui Fan;Xinyu Zhang;Haozhu Pei;Zhaoxiang Wei;Junhou Cao;Xudong Zhu;Jiaxing Wei;Siyang Liu;Weifeng Sun","doi":"10.1109/LED.2025.3584419","DOIUrl":"https://doi.org/10.1109/LED.2025.3584419","url":null,"abstract":"The reliability of the low-barrier Poly-Si/4H-SiC heterojunction is experimentally demonstrated for the first time, with a superior long-term forward conduction and reverse blocking reliability under the 500-A/cm2 forward current density and the 1-MV/cm reverse electric field, respectively, which is critical for power applications. The pure power heterojunction is fabricated on a 1.2 kV-class 4H-SiC epilayer, featuring a barrier height of 0.804 eV and a great ideality factor of 1.026. It is innovatively discovered that the heterojunction reverse current (<inline-formula> <tex-math>${I}_{text {R}}text {)}$ </tex-math></inline-formula> anomalously decreases with the reverse bias stress time without any forward electrical parameter degradation. By modelling the heterojunction field-emission (FE) tunneling and extracting the defect density, it is demonstrated that the deep-level acceptor-type interface defects are activated by the reverse electric field, which will capture electrons and impede the reverse FE tunneling current. The research results can promote the power applications of the Poly-Si/4H-SiC heterojunction and provide guidelines for all heterojunction devices in the burn-in process and the reliability evaluation.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1489-1492"},"PeriodicalIF":4.5,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Gate Misalignment on Analog Performance Metrics of Nanoscale Independent Dual-Gate IGZO FETs for BEOL-Memory Sense Amplifier Design 栅极失调对用于beol -记忆感测放大器设计的纳米级独立双栅IGZO fet模拟性能指标的影响

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584150

Xiaoyi Zhang;Kaifei Chen;Xufan Li;Yue Zhao;Kexin Shang;Guanhua Yang;Lingfei Wang;Ling Li

{"title":"Impact of Gate Misalignment on Analog Performance Metrics of Nanoscale Independent Dual-Gate IGZO FETs for BEOL-Memory Sense Amplifier Design","authors":"Xiaoyi Zhang;Kaifei Chen;Xufan Li;Yue Zhao;Kexin Shang;Guanhua Yang;Lingfei Wang;Ling Li","doi":"10.1109/LED.2025.3584150","DOIUrl":"https://doi.org/10.1109/LED.2025.3584150","url":null,"abstract":"For high-density 3D DRAM, the voltage drops of Through-Silicon-Via are nonnegligible among stacks of layers, requiring high-gain sense amplifier (SA) design. Considering back-end of line (BEOL) compatibility, independent dual-gate (IDG) IGZO FETs are promising not only for multi-bit DRAM design but also for applications in SA input transistors. This letter investigates the important analog figures of merit (FOMs) of DG IGZO FETs under various operating conditions. TCAD simulations validated by experimental data reveal that top-gate misalignment (ranging from 25% to 100%) exhibits electric field distribution variations. The trade-off between transconductance generation factor and intrinsic gain is obviously observed. Such a top-gate misalignment effect causes threshold voltage shifts and circuit mismatches in DRAM SAs, and the mismatch can be compensated by independent top-gate biasing, enabling threshold voltage modulation. IDG IGZO FETs indicate superior gain performance compared to single-gate IGZO FETs and lower leakage current than Si-based FETs, which are critical for SA input transistors. These findings provide important guidance for optimizing dual-gate IGZO FETs in analog applications, particularly for BEOL-memory SAs that need both high gain and fast response speed.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1652-1655"},"PeriodicalIF":4.5,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low Von β -Ga₂O₃ Schottky Diodes With Synergistic Suppression of Bulk and Perimeter Leakage 协同抑制体积泄漏和周长泄漏的低Von β -Ga₂O₃肖特基二极管

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584109

Zhao Han;Weibing Hao;Qiuyan Li;Junpeng Wen;Lequan Wang;Xuanze Zhou;Guangwei Xu;Shu Yang;Shibing Long

{"title":"Low Von β -Ga₂O₃ Schottky Diodes With Synergistic Suppression of Bulk and Perimeter Leakage","authors":"Zhao Han;Weibing Hao;Qiuyan Li;Junpeng Wen;Lequan Wang;Xuanze Zhou;Guangwei Xu;Shu Yang;Shibing Long","doi":"10.1109/LED.2025.3584109","DOIUrl":"https://doi.org/10.1109/LED.2025.3584109","url":null,"abstract":"This work first presents <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 trench Schottky barrier controlled Schottky diodes (TSBSDs) with low turn-on voltage (<inline-formula> <tex-math>${V}_{text {on}}text {)}$ </tex-math></inline-formula> and substantially improved blocking performance. The high Schottky barrier formed by PtOx and <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 in the trench region can pinch off and shield the tungsten (W) contact region with low barrier, thereby effectively suppressing reverse bulk leakage. In addition, the composite mesa and junction termination extension (MJTE) is used to alleviate the perimeter leakage caused by edge electric field crowding. The fitting and analysis of leakage current versus radius in logarithmic scale is demonstrated to identify the location that dominates leakage. As a result, the leakage is reduced by more than three orders of magnitude owing to the synergistic suppression of bulk and perimeter leakage. Meanwhile, the breakdown voltage increases from 458 V to 1466 V, with a low <inline-formula> <tex-math>${V}_{text {on}}$ </tex-math></inline-formula> maintained at 0.71 V. In additionally, the TSBSD featuring MJTE maintains the lowest power loss in most duty cycles benefiting from the low <inline-formula> <tex-math>${V}_{text {on}}$ </tex-math></inline-formula> and leakage current. This work paves the way to improve the operational efficiency of <inline-formula> <tex-math>$boldsymbol {beta }$ </tex-math></inline-formula>-Ga2O3 Schottky diodes.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1497-1500"},"PeriodicalIF":4.5,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Photocarrier-Driven Passive Modulation for III-Nitride Optoelectronic System iii -氮化物光电系统的光载流子驱动无源调制

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584290

Hao Zhang;Ziqi Ye;Meixin Feng;Qian Sun;Yongjin Wang

引用次数: 0

Distinctive Quantum Confinement Characteristic of 3 nm Gate-All-Around (GAA) PMOS Multi-Bridge-Channel-FET (MBCFET) 3nm栅极全能（GAA） PMOS多桥通道场效应管（MBCFET）的独特量子约束特性

IF 4.5 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI: 10.1109/LED.2025.3584056

Hyungwoo Ko;Jooyoung Song;Sungjoon Park;Sugwon Yu;Jinho Choi;Hyeongsub Song;Seunghyun Noh;Sungjae Lee

引用次数: 0