IEEE Electron Device Letters最新文献_第9页

Miniaturized On-Chip Bandpass Filter With Multi-Transmission Zeros Using Interwound Winding Transformer 采用绕线绕组变压器的微型化片上多传输零带通滤波器

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-10 DOI: 10.1109/LED.2025.3549368

Chang Xu;Xiaolong Wang;Cong Wang;Geyu Lu

{"title":"Miniaturized On-Chip Bandpass Filter With Multi-Transmission Zeros Using Interwound Winding Transformer","authors":"Chang Xu;Xiaolong Wang;Cong Wang;Geyu Lu","doi":"10.1109/LED.2025.3549368","DOIUrl":"https://doi.org/10.1109/LED.2025.3549368","url":null,"abstract":"In this letter, a miniaturized on-chip bandpass filter (BPF) with multi-transmission zeros (TZs) is proposed in the gallium arsenide (GaAs)-based integrated passive device (IPD) technology. The proposed BPF consists of two symmetrical LC ring structures, which are connected by an interwound winding transformer (IWT). Three TZs are newly created by coupling capacitors between two interwound spiral inductors in IWT without adding extra circuit components. Through even- and odd-mode analysis, general simultaneous equations for the circuit parameters are newly derived. Two TZs in the upper stopband can be significantly tuned by adjusting the extra variable parameter (<inline-formula> <tex-math>${L}_{{1}}$ </tex-math></inline-formula>) without affecting passband performance. Considering the trade-off between achievable coupling factor, coupling capacitor and performance, narrower bandwidths are preferred for better RL and SR in fabrication. For validation, a prototype filter with a 3-dB fractional bandwidth (FBW) of 48.5% (3.9-6.4 GHz) is manufactured in GaAs-IPD technology. The measured BPF exhibits multi-TZs in the stopband and insertion loss is 2.25 dB at the center frequency <inline-formula> <tex-math>${f}_{{0}} = 5$ </tex-math></inline-formula> GHz. The filter has a compact size of <inline-formula> <tex-math>$0.016 ; lambda _{{0}} times 0.007 ; lambda _{{0}}$ </tex-math></inline-formula>, where <inline-formula> <tex-math>$lambda _{{0}}$ </tex-math></inline-formula> is the wavelength in air at <inline-formula> <tex-math>${f}_{{0}}$ </tex-math></inline-formula>.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"713-716"},"PeriodicalIF":4.1,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

P-Type SnO Thin-Film Transistor With Scaled Channel Lengths for High-Density Monolithic Integration in Complementary Logic Circuits Applications 可缩放通道长度的p型SnO薄膜晶体管在互补逻辑电路中的高密度单片集成应用

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-10 DOI: 10.1109/LED.2025.3549439

Tsung-Che Chiang;Zhen-Hao Li;Cheng-Wei Wang;Pei-Yun Huang;Jo-Lin Chen;Yu-Ming Zhang;Yao-Chen Chien;Kai-Cheng Syu;You-Syuan Zhou;Po-Tsun Liu

{"title":"P-Type SnO Thin-Film Transistor With Scaled Channel Lengths for High-Density Monolithic Integration in Complementary Logic Circuits Applications","authors":"Tsung-Che Chiang;Zhen-Hao Li;Cheng-Wei Wang;Pei-Yun Huang;Jo-Lin Chen;Yu-Ming Zhang;Yao-Chen Chien;Kai-Cheng Syu;You-Syuan Zhou;Po-Tsun Liu","doi":"10.1109/LED.2025.3549439","DOIUrl":"https://doi.org/10.1109/LED.2025.3549439","url":null,"abstract":"This work successfully developed an optimized p-type oxide semiconductor thin-film transistor (TFT) using an 8 nm-thick tin monoxide (SnO) channel. The device shows a high hole mobility of ~2 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, an on-off current ratio (ION/I<inline-formula> <tex-math>${}_{text {OFF}}text {)}$ </tex-math></inline-formula> over <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula>, and a subthreshold swing (S.S.) of less than 0.3 V/decade. When the channel length (L<inline-formula> <tex-math>${}_{text {CH}}text {)}$ </tex-math></inline-formula> is reduced to 100 nm, the devices achieve high drain current density, a low S.S. of ~0.3 V/dec, and a near-enhancement mode threshold voltage (V<inline-formula> <tex-math>${}_{text {TH}}text {)}$ </tex-math></inline-formula> of 0.18 V. Additionally, short-channel transistors, including ITO n-TFT and SnO p-TFT, were integrated through a bottom-up fabrication approach to create full-oxide complementary logic circuits, such as inverters and NAND gates, within a monolithic three-dimensional (M3D) architecture. These circuits demonstrate excellent performance, including a high voltage gain of 73 V/V at V<inline-formula> <tex-math>${}_{text {DD}}=3.6$ </tex-math></inline-formula> V and a large noise margin (NMH/NM<inline-formula> <tex-math>${}_{text {L}}text {)}$ </tex-math></inline-formula> of 1.14 V/1.12 V at V<inline-formula> <tex-math>${}_{text {DD}}=2.8$ </tex-math></inline-formula> V. The fabrication is compatible with back-end-of-line (BEOL) process and operates under a low thermal budget, making it promising for M3D integrated circuits (M3D-ICs).","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"769-772"},"PeriodicalIF":4.1,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Tunable Synaptic Transistor With Volatile and Non-Volatile Switching Capabilities for Hierarchical Data Processing 具有易失性和非易失性开关能力的可调谐突触晶体管用于分层数据处理

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-10 DOI: 10.1109/LED.2025.3549491

Guocheng Zhang;Hongyu Wang;Shixian Qin;Jianchuan Tang;Zili Zeng;Changqiang Su;Xin Yi;Xianghong Zhang;Huipeng Chen

引用次数: 0

Multiple-Independent-Gate Reconfigurable FETs Processed on Industrial 300 mm FDSOI 在工业300mm FDSOI上加工的多独立栅极可重构场效应管

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-10 DOI: 10.1109/LED.2025.3549531

N. Bhattacharjee;Y. He;G. Galderisi;V. Havel;S. Slesazeck;V. Sessi;M. Drescher;M. Zier;M. Simon;K. Ruttloff;K. Li;A. Zeun;A.-S. Seidel;C. Metze;M. Grothe;S. Jansen;J. Hoentschel;T. Mikolajick;J. Trommer

{"title":"Multiple-Independent-Gate Reconfigurable FETs Processed on Industrial 300 mm FDSOI","authors":"N. Bhattacharjee;Y. He;G. Galderisi;V. Havel;S. Slesazeck;V. Sessi;M. Drescher;M. Zier;M. Simon;K. Ruttloff;K. Li;A. Zeun;A.-S. Seidel;C. Metze;M. Grothe;S. Jansen;J. Hoentschel;T. Mikolajick;J. Trommer","doi":"10.1109/LED.2025.3549531","DOIUrl":"https://doi.org/10.1109/LED.2025.3549531","url":null,"abstract":"Reconfigurable Field Effect Transistors are emerging devices able to extend CMOS circuit functionality, since they can be operated as either n-type or p-type transistors. In this work, we demonstrate the fabrication of RFETs with multiple independent top gates on an industrial fully-depleted silicon-on-insulator technology featuring an ultra-thin buried oxide. The devices are fabricated using industrial 300 mm CMOS processes including the complete back-end-of-line. Two different RFET variants, featuring two and three independent top gates, are presented and their operation is analyzed. Electrical characteristics are discussed in detail, reporting larger than 106 on/off ratios, off-state currents as low as 10 pA/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, and minimal subthreshold swings below 90 mV/dec, depending on the operation mode. Exploiting the body bias option offered by the FDSOI channels, we show that it is possible to boost the individual device performance, thus obtaining high on-state current densities of 32 (35) <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m for n-type (p-type) operation.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"689-692"},"PeriodicalIF":4.1,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Linear Fine-Tuning VFB and Improved Interface via Novel Al₂O₃ Atomic in-situ Dipole Buffer Layer (DBL) in ALD La₂O₃ Dipole-First Stack ALD La₂O₃偶极子优先叠加中新型Al₂O₃原子原位偶极子缓冲层（DBL）的线性微调VFB和改进界面

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-07 DOI: 10.1109/LED.2025.3549003

Yanzhao Wei;Jiaxin Yao;Yu Wang;Qingzhu Zhang;Jianfeng Gao;Xiaolei Wang;Jun Luo;Huaxiang Yin

引用次数: 0

p-NiO/LiNiO-GaN Heterojunctions: A Potential Alternative to p-GaN for Advanced Devices p-NiO/LiNiO-GaN异质结：先进器件中p-GaN的潜在替代品

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-07 DOI: 10.1109/LED.2025.3549252

Zheng Hao;Alessandro Floriduz;Yuan Zong;Uiho Choi;Mounir Mensi;Elison Matioli

{"title":"p-NiO/LiNiO-GaN Heterojunctions: A Potential Alternative to p-GaN for Advanced Devices","authors":"Zheng Hao;Alessandro Floriduz;Yuan Zong;Uiho Choi;Mounir Mensi;Elison Matioli","doi":"10.1109/LED.2025.3549252","DOIUrl":"https://doi.org/10.1109/LED.2025.3549252","url":null,"abstract":"In this work, we introduce a p-NiO/LiNiO stack grown via low-temperature deposition processes, offering an effective alternative for creating localized p-type regions in GaN devices. This stack combines a high hole concentration p-NiO film ([h] <inline-formula> <tex-math>$= 2times 10^{{19}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-{3}}$ </tex-math></inline-formula>) with an epitaxially crystalline p-LiNiO film, resulting in a high-quality p-type layer that can be flexibly deposited and patterned on GaN devices. Here, we investigate the transport and breakdown properties of the p-NiO/LiNiO-GaN heterojunction by fabricating a p-NiO/LiNiO-GaN PiN diode. The PiN diode exhibited excellent electrical performance, including a low turn-on voltage (<inline-formula> <tex-math>${V} _{text {ON}}$ </tex-math></inline-formula>) of 1.7 V, a low specific on-state resistance (R<inline-formula> <tex-math>${}_{text {ON},text {sp}}$ </tex-math></inline-formula>) of 1.15 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2, and a high breakdown voltage (BV) exceeding 1000 V, comparable to those achieved with epitaxial GaN homojunctions. These results highlight the potential of utilizing conductive and compatible p-NiO/LiNiO stacks to replace p-GaN for high-quality localized p-n junctions, simplifying the manufacturability of GaN-based devices and enabling advanced device concepts where p-GaN is challenging to be implemented.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"729-732"},"PeriodicalIF":4.1,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Characterization and Design of AlN/GaN/AlN HEMTs on Foreign Substrates 国外衬底上AlN/GaN/AlN hemt的热特性与设计

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-06 DOI: 10.1109/LED.2025.3548853

Seokjun Kim;Eungkyun Kim;Husam Walwil;Daniel C. Shoemaker;Jimy Encomendero;Matthew T. DeJarld;Maher B. Tahhan;Eduardo M. Chumbes;Jeffrey R. Laroche;Debdeep Jena;Huili G. Xing;Sukwon Choi

引用次数: 0

Bi-Mode Inverse Design of 3D Structures for MEMS Resonators MEMS谐振器三维结构的双模逆设计

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-06 DOI: 10.1109/LED.2025.3548612

Binzhou Zuo;Zeyu Wu;Junyuan Zhao;Bo Niu;Yumo Lei;Lixin Cao;Yinfang Zhu;Jinling Yang

{"title":"Bi-Mode Inverse Design of 3D Structures for MEMS Resonators","authors":"Binzhou Zuo;Zeyu Wu;Junyuan Zhao;Bo Niu;Yumo Lei;Lixin Cao;Yinfang Zhu;Jinling Yang","doi":"10.1109/LED.2025.3548612","DOIUrl":"https://doi.org/10.1109/LED.2025.3548612","url":null,"abstract":"This work presents an automated algorithm for MEMS resonator structure generation based on inverse design, integrating deep learning and neural networks to predict key physical properties, including resonance frequency (f), quality factor of thermoelastic damping (Q<inline-formula> <tex-math>${}_{textit {TED}}$ </tex-math></inline-formula>), and motional impedance (Rx). Unlike traditional methods relying on finite element analysis (FEA), this approach leverages a database-driven deep learning model, achieving prediction speeds 9,740 times faster than the conventional FEA software with an average accuracy of 97.5%, 96.5%, 96.4 for f, Q<inline-formula> <tex-math>${}_{textit {TED}}$ </tex-math></inline-formula> and Rx,respectively. The algorithm supports flexural and Lamé modes and could generate resonators with a broad frequency range from ~8 to ~63 MHz, significantly surpassing existing methods. By efficiently predicting seed structures, the method guides the inverse design process, generating high Q, and low Rx resonator structures within 10 minutes. The generated devices exhibit deviations of less than 3% from target performance metrics. Simulations and experimental results validate the feasibility and effectiveness of the proposed algorithm, highlighting its potential for accelerating MEMS design with enhanced performance and precision.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"841-844"},"PeriodicalIF":4.1,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stabilizing ALD Ultrathin In₂O₃ TFTs Under High Humidity Ambient by an Added IGZO Layer 通过添加IGZO层稳定高湿环境下的ALD超薄In₂O₃TFTs

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-06 DOI: 10.1109/LED.2025.3548694

Shanshan Ju;Jinxiong Li;Yupu Tang;Wei Qian;Fangxing Zhang;Jianzhang Zhu;Xu Tian;Songjie Yang;Lining Zhang;Lei Lu;Shengdong Zhang;Xinwei Wang

引用次数: 0

Damage-Free Neutral Beam Etching for Gate Recess in E-Mode AlGaN/GaN HEMTs E-Mode AlGaN/GaN hemt中栅极凹槽的无损伤中性束刻蚀

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-06 DOI: 10.1109/LED.2025.3548676

Yi-Ho Chen;Fu-Chuan Chu;Muhammad Aslam;Yao-Jen Lee;Yiming Li;Seiji Samukawa

引用次数: 0