IEEE Electron Device Letters最新文献_第8页

IEEE Electron Device Letters Publication Information IEEE电子器件通讯出版信息

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-07-28 DOI: 10.1109/LED.2026.3709231

引用次数: 0

The Ballistic Injection in IGZO GAA VFET With Scaled Source/Drain Extension and Its Impact on On-Current Enhancement 源极/漏极扩展IGZO GAA VFET的弹道注入及其对导通电流增强的影响

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-06-24 DOI: 10.1109/LED.2026.3706796

Liankai Zheng;Ziheng Wang;Zhiyu Lin;Mengwei Si

{"title":"The Ballistic Injection in IGZO GAA VFET With Scaled Source/Drain Extension and Its Impact on On-Current Enhancement","authors":"Liankai Zheng;Ziheng Wang;Zhiyu Lin;Mengwei Si","doi":"10.1109/LED.2026.3706796","DOIUrl":"https://doi.org/10.1109/LED.2026.3706796","url":null,"abstract":"In this work, the impact of source/drain (S/D) extension scaling on the performance of indium-gallium-zinc oxide (IGZO) gate-all-around (GAA) vertical field-effect transistors (VFETs) is systematically studied both theoretically and experimentally. The electron transport at the S/D extension is investigated by drift-diffusion (DD) simulation and ballistic injection simulation. It is observed that the I-V characteristics at high VDS of IGZO GAA VFET with scaled S/D extension deviate significantly from the velocity saturation model due to the electron velocity overshoot at the S/D extension region. A ballistic injection model is introduced that can well explain the experimental I-V characteristics. It is found that the S extension scaling, rather than the D extension scaling, is more effective for on-current (I<inline-formula> <tex-math>${}_{text {on}}text {)}$ </tex-math></inline-formula> enhancement. By S extension scaling (down to 5 nm), the Ion enhancement is demonstrated experimentally, showing a high Ion of <inline-formula> <tex-math>$569~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m (V<inline-formula> <tex-math>${}_{text {D}} =2.2$ </tex-math></inline-formula> V).","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1587-1590"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Seed-Iteration-Epitaxy Technique Achieving High-Mobility Poly-Si Channel for BEOL-Compatible Three-Dimensional Integration 种子迭代外延技术实现高迁移率多晶硅通道兼容beol三维集成

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-06-26 DOI: 10.1109/LED.2026.3705796

Jinbiao Liu;Xianglie Sun;Zhuo Chen;Jianfeng Gao;Xiaobin He;Wenjuan Xiong;Chenchen Zhang;Junfeng Li;Chao Zhao;Shujuan Mao;Jun Luo

{"title":"Seed-Iteration-Epitaxy Technique Achieving High-Mobility Poly-Si Channel for BEOL-Compatible Three-Dimensional Integration","authors":"Jinbiao Liu;Xianglie Sun;Zhuo Chen;Jianfeng Gao;Xiaobin He;Wenjuan Xiong;Chenchen Zhang;Junfeng Li;Chao Zhao;Shujuan Mao;Jun Luo","doi":"10.1109/LED.2026.3705796","DOIUrl":"https://doi.org/10.1109/LED.2026.3705796","url":null,"abstract":"In this work, we demonstrate a back-end-of-line (BEOL)-compatible seed-iteration-epitaxy (SIE) technique, achieving high-quality Si crystallization with a grain size of <inline-formula> <tex-math>$1.83~mu $ </tex-math></inline-formula>m and an integrity factor of 0.9. The SIE technique consists of two sequential steps: (1) grain-filter (GF)-based seed preparation to form high-quality poly-Si seeds and (2) seed-assisted crystallization, where liquid phase epitaxy (LPE)-like growth occurs using the underlying seeds as templates. At the device level, by utilizing the SIE approach, excellent electrical performance is achieved for NMOS, showing ON-OFF current ratio (<inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}text {)}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$2.1times 10^{{7}}$ </tex-math></inline-formula>, subthreshold swing (<italic>SS) of 82.8 mV/dec, and field-effect mobility (<inline-formula> <tex-math>$mu _{text {FE}}text {)}$ </tex-math></inline-formula> of 605 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s. This approach provides a promising pathway for integrating high-mobility channel materials with potential relevance to future three-dimensional integration and memory applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1627-1630"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Changes to the Editorial Board 编辑委员会的变动

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-07-28 DOI: 10.1109/LED.2026.3707329

Kelin J. Kuhn

引用次数: 0

On-Chip Integrated CsPbBr3 Sheet-Cathode Vacuum Nanodiode for Direct Electron Irradiation Detection 片上集成CsPbBr3片阴极真空纳米二极管用于直接电子辐射检测

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-06-02 DOI: 10.1109/LED.2026.3699323

Xiaohang Long;Yang Chen;Yifeng Huang;Zairan Liu;Guichen Song;Jun Chen;Shaozhi Deng;Fei Liu;Juncong She

引用次数: 0

CMP-Free Organic Hybrid Bonding Based on Mechanical Interlock Structure via Surface Treatments for 3-D Integration 基于机械联锁结构的无cmp有机杂化键结合表面处理的三维集成

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-07-28 DOI: 10.1109/LED.2026.3704582

Jinzhu Li;Qicun Lou;Xinyao Wang;Mingze Ban;Wenchao Wang;Ziyu Liu;Hao Zhu;Qingqing Sun;Lin Chen;Yabin Sun;David Wei Zhang

{"title":"CMP-Free Organic Hybrid Bonding Based on Mechanical Interlock Structure via Surface Treatments for 3-D Integration","authors":"Jinzhu Li;Qicun Lou;Xinyao Wang;Mingze Ban;Wenchao Wang;Ziyu Liu;Hao Zhu;Qingqing Sun;Lin Chen;Yabin Sun;David Wei Zhang","doi":"10.1109/LED.2026.3704582","DOIUrl":"https://doi.org/10.1109/LED.2026.3704582","url":null,"abstract":"Conventional hybrid bonding relies heavily on chemical mechanical polishing (CMP) to achieve ultra-fine surface planarity, and this reliance significantly restricts the scalability and reliability of the integration process. This work proposes a CMP-free hybrid bonding strategy named Mechanical Interlock Bonding-Hybrid (MIB-H) that combines a ‘Cu protrusion-Polyimide (PI) recess’ interlocking structure. However, the bonding quality of this interlocking structure depends critically on the surface treatment during the pre-bonding stage. Specifically, the inherent property mismatch between hydrophobic PI and oxidation-prone Cu leads to poor interfacial reactivity and promotes void and defect formation. Therefore, through the synergistic treatment of Ar plasma activation and citric acid immersion, a hydroxyl (−OH) active layer was successfully formed simultaneously on the surfaces of Cu/Ti, PI, and SiO2. Additionally, the increased total surface area provides more adsorption sites for -OH groups. Based on this, the Cu/Ti/Cu interface achieved at 250°<bold>C exhibits sufficient atomic diffusion. Notably, the 0. <bold>5 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula><bold>mgaps reserved between Cu and PI in the interlocking structure have disappeared, which is attributed to the expansion of PI filling the gaps at high temperatures. This Cu/PI interlocking structure based on the co-hydroxylation strategy shows great potential for high-density heterogeneous chip integration.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1623-1626"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wide-Temperature-Range Stable Memristor PUF Using WS2/Graphene Heterostructure 基于WS2/石墨烯异质结构的宽温程稳定忆阻器PUF

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-06-18 DOI: 10.1109/LED.2026.3703953

Yuan Cao;Ya Su;Zhao Huang;Tianao Liu;Xi Wan;Yu Liu;Hangyufei Zhang

{"title":"Wide-Temperature-Range Stable Memristor PUF Using WS2/Graphene Heterostructure","authors":"Yuan Cao;Ya Su;Zhao Huang;Tianao Liu;Xi Wan;Yu Liu;Hangyufei Zhang","doi":"10.1109/LED.2026.3703953","DOIUrl":"https://doi.org/10.1109/LED.2026.3703953","url":null,"abstract":"This letter presents a novel physical unclonable function (PUF) based on WS2/Graphene heterostructured memristors, where a sulfur-deficient WS2 layer is confined within a two-dimensional (2D) heterostructure. This tailored layer endows the memristors with superior thermally stable resistive switching and consistent entropy generation over a wide temperature range. Hybrid physical entropy, which is derived from fabrication-induced random spatial distributions of defect states and sulfur vacancies, plus residual conductive filament (CF) configurations, ensures highly reliable secret key generation. An <inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula> memristor array is fabricated and characterized, and a differential voltage-based readout scheme in the 1T1R architecture is employed to suppress common-mode variations. Experimental results demonstrate that the proposed PUF exhibits excellent entropy stability and anti-interference capability, and long-term endurance (<inline-formula> <tex-math>${10}^{{6}}$ </tex-math></inline-formula> SET/RESET cycles) across <inline-formula> <tex-math>$-{100}~^{circ } text {C}$ </tex-math></inline-formula> to <inline-formula> <tex-math>${250}~^{circ } text {C}$ </tex-math></inline-formula> with an ultra-low intra-chip Hamming distance (Intra-HD) of 0.68%. It is promising for industrial and security electronics operating under harsh conditions.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1667-1670"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Electron Device Letters Information for Authors IEEE电子器件通讯作者信息

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-07-28 DOI: 10.1109/LED.2026.3709237

引用次数: 0

Changes to the Editorial Board 编辑委员会的变动

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-07-28 DOI: 10.1109/LED.2026.3707332

Kelin J. Kuhn

引用次数: 0

Enhanced Disturbance Immunity in Ferroelectric FETs Using La-Doped HfO2 Film la掺杂HfO2薄膜增强铁电场效应管的抗扰性

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-08-01 Epub Date: 2026-06-17 DOI: 10.1109/LED.2026.3703446

Sheung Hun Kim;Youngkeun Park;Batzorig Buyantogtokh;Jaejoong Jeong;Chanmi Yu;Seungbum Hong;Byung Jin Cho

引用次数: 0