IEEE Electron Device Letters最新文献_第2页

Location-Selective Dual Work-Function Engineering for DRAM Vertical Cell Transistors DRAM垂直单元晶体管的位置选择双工作功能工程

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-24 DOI: 10.1109/LED.2026.3726492

Dongsik Kong;Hoin Lee;Jae-Hyun Lee;Jongwook Jeon

{"title":"Location-Selective Dual Work-Function Engineering for DRAM Vertical Cell Transistors","authors":"Dongsik Kong;Hoin Lee;Jae-Hyun Lee;Jongwook Jeon","doi":"10.1109/LED.2026.3726492","DOIUrl":"https://doi.org/10.1109/LED.2026.3726492","url":null,"abstract":"As dynamic random-access memory (DRAM) technology approaches the scaling limit of conventional 6F2 buried-channel array transistor (BCAT) structures, vertical cell transistors (VCTs) have emerged as promising candidates for future 4F2 DRAM architectures. In this work, a location-selective Dual Work-Function (DWF) engineering scheme is proposed to co-optimize leakage and drive-current characteristics in VCT devices. Using calibrated three-dimensional TCAD simulations, lower-work-function n+ polysilicon regions were selectively introduced into the front-gate (FG) and back-gate (BG) electrodes. In the buried contact (BC)-side DWF implementation, the local gate electrostatics near the BC junction were modulated, thereby reducing the peak electric field responsible for gate-induced drain leakage (GIDL). The FG_BC DWF reduced GIDL current by up to 66% while maintaining a threshold voltage (V<inline-formula> <tex-math>${}_{text {T}}text {)}$ </tex-math></inline-formula> shift below 10 mV and less than 1% variation in ON-current. In the bit line (BL)-side DWF implementation, the reduced work function lowered the electron injection barrier near the BL-side carrier-injection region, leading to ON-current enhancement of up to 12.6% while maintaining nearly unchanged VT and subthreshold swing (SS). In addition, a combined FG_BC+BG_BL structure demonstrated concurrent GIDL suppression and ON-current enhancement without additional WL resistance overhead. These results indicate that location-selective DWF engineering, enabled by the vertically separated BC-side and BL-side junctions, provides a promising design guideline for low-leakage and high-performance 4F2 DRAM VCTs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2047-2050"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Complementary Self-Selective Memristor for Intrinsic Differential Behavior 互补自选择忆阻器的内在微分行为

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-27 DOI: 10.1109/LED.2026.3724679

Xuemeng Fan;Guobin Zhang;Zijian Wang;Zhejia Zhang;Qi Luo;Wenjue Zhou;Haoxiang Yu;Haoze Yu;Xiaolei Zhu;Yishu Zhang

{"title":"Complementary Self-Selective Memristor for Intrinsic Differential Behavior","authors":"Xuemeng Fan;Guobin Zhang;Zijian Wang;Zhejia Zhang;Qi Luo;Wenjue Zhou;Haoxiang Yu;Haoze Yu;Xiaolei Zhu;Yishu Zhang","doi":"10.1109/LED.2026.3724679","DOIUrl":"https://doi.org/10.1109/LED.2026.3724679","url":null,"abstract":"Memristor-based in-memory computing relies on differential pairs for signed weights and suffers from sneak paths, large area, and device mismatch. Here, we present a novel memristor device with intrinsic differential characteristics enabling bidirectional weight tuning, offering a promising pathway toward high-efficiency in-memory computing with great potential for in-situ learning. The device exhibits a self-rectification ratio and nonlinearity of <inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula> under both polarities, with an endurance exceeding <inline-formula> <tex-math>$10^{{6}}$ </tex-math></inline-formula> cycles. Under pulse programming, bidirectional potentiation and depression are realized, enabling intrinsic positive and negative conductance modulation within a single device. By tuning the bidirectional conductance asymmetry via pulses, single-device-level differential computation is achieved, suppressing conductance drift and circumventing the inherent non-uniformity of dual-device architectures. We experimentally achieve low-error differential weight updates on a <inline-formula> <tex-math>${32}times {32}$ </tex-math></inline-formula> crossbar array. The device’s native bipolar conductance supports differential readout, potentially removing the need for independent subtraction hardware and providing a novel optimization route for in-situ learning CIM.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2011-2014"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 3-D Stackable 1T2C DRAM With Sidewall Storage Capacitors for High-Density Memory 用于高密度存储器的带侧壁存储电容的3-D可堆叠1T2C DRAM

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-26 DOI: 10.1109/LED.2026.3722499

Ruifeng Tang;Xuedong Zhao;Chuanli Zhang;Xun Yu;Guangxiang Fan;Yifan Zhang;Pengfei Jiang;Xiao Long;Yuan Wang;Yang Yang;Tiancheng Gong;Yan Wang;Wei Wei;Qing Luo

{"title":"A 3-D Stackable 1T2C DRAM With Sidewall Storage Capacitors for High-Density Memory","authors":"Ruifeng Tang;Xuedong Zhao;Chuanli Zhang;Xun Yu;Guangxiang Fan;Yifan Zhang;Pengfei Jiang;Xiao Long;Yuan Wang;Yang Yang;Tiancheng Gong;Yan Wang;Wei Wei;Qing Luo","doi":"10.1109/LED.2026.3722499","DOIUrl":"https://doi.org/10.1109/LED.2026.3722499","url":null,"abstract":"This work proposes a 3D Stackable 1T2C DRAM architecture for high-density memory applications. Unlike conventional 1T1C DRAM with large lateral storage capacitors, the proposed structure integrates capacitors along the sidewalls of the vertically stacked cells. The device is implemented with a NAND-like process flow based on alternating metal/insulator stacks, lateral replacement, and a vertical common bit-line connection, enabling compact multilayer integration. An amorphous oxide semiconductor channel is employed to suppress off-state leakage. TCAD simulations verify the write, hold, and read operations of the proposed cell. A bit-line sensing margin exceeding 350 mV and retention time exceeding 100 s is obtained with a bit-line load capacitance of 10 fF. In addition, a two-layer stacked cell simulation demonstrates independent write and read operations without observable crosstalk. With hexagonal close packing, the projected storage density can reach 0.024 Gb/mm2 per layer. These results indicate that the proposed 3D 1T2C DRAM is a promising candidate for high-density memory.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2035-2038"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Changes to the Editorial Board 编辑委员会的变动

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3707714

Kelin J. Kuhn

引用次数: 0

EDS Meetings Calendar EDS会议日程表

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3731835

引用次数: 0

Humidity-Modulated Flexible Chitosan-Based Memristor With Synaptic Behavior 具有突触行为的湿度调制柔性壳聚糖基忆阻器

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-20 DOI: 10.1109/LED.2026.3725255

Yiwen Chao;Yan Zhang;Ruipeng Wang;Yang Dai;Wu Zhao

{"title":"Humidity-Modulated Flexible Chitosan-Based Memristor With Synaptic Behavior","authors":"Yiwen Chao;Yan Zhang;Ruipeng Wang;Yang Dai;Wu Zhao","doi":"10.1109/LED.2026.3725255","DOIUrl":"https://doi.org/10.1109/LED.2026.3725255","url":null,"abstract":"A flexible Cu/Ti/chitosan:sodium chloride (CS:NaCl)/indium tin oxide (ITO)/polyimide (PI) memristor was evaluated at controlled relative humidity (RH) levels of 30% and 60% to investigate what RH-dependent changes occur in nonvolatile switching and short-term synaptic responses. Across five independently fabricated devices, the mean SET voltage (V<inline-formula> <tex-math>${}_{text {SET}}text {)}$ </tex-math></inline-formula> increased from <inline-formula> <tex-math>$2.128~pm ~0.046$ </tex-math></inline-formula> to <inline-formula> <tex-math>$3.152~pm ~0.046$ </tex-math></inline-formula> V, whereas the RESET voltage (V<inline-formula> <tex-math>${}_{text {RESET}}text {)}$ </tex-math></inline-formula> showed greater cycle-to-cycle and device-to-device variability. Higher RH enhanced the excitatory postsynaptic current, paired-pulse facilitation (PPF), and low-voltage conductance modulation. A 30%<inline-formula> <tex-math>$to 60$ </tex-math></inline-formula>%<inline-formula> <tex-math>$to 30$ </tex-math></inline-formula>% RH sequence showed a recovery trend in the SET voltage, and bipolar switching remained observable in all five devices after 200 bending cycles at R = 6 mm. Based on the measured conductance modulation, MNIST recognition exceeded 92% at both RH levels. Fusing I–V and PPF classifier outputs enabled proof-of-concept RH-state classification. These results reveal differentiated RH modulation of nonvolatile SET and short-term synaptic responses in a flexible chitosan-based memristor.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2039-2042"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Fabrication of High-Breakdown InGaAs APDs With MOCVD Zn-Diffused Guard Rings MOCVD扩散锌保护环高击穿InGaAs apd的设计与制造

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-20 DOI: 10.1109/LED.2026.3724580

Sung Un Baek;Phuong Nam Tran;Tran Anh Thu Nguyen;Minh Tuan Phan;Sung Jin Kim;Dong Hwan Jun;Jae Cheol Shin

引用次数: 0

A Bio-Inspired Visual System With Single-Spike Coding Based on VO2 Memristors 基于VO2忆阻器的单尖峰编码仿生视觉系统

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-01 DOI: 10.1109/LED.2026.3723903

Bohao Jin;Fudi Wang;Ai Chen;Kai Ma;Jiening Wu;Shukai Duan;Lidan Wang;Teng Zhang;Yingming Lu;Rui Yuan

{"title":"A Bio-Inspired Visual System With Single-Spike Coding Based on VO2 Memristors","authors":"Bohao Jin;Fudi Wang;Ai Chen;Kai Ma;Jiening Wu;Shukai Duan;Lidan Wang;Teng Zhang;Yingming Lu;Rui Yuan","doi":"10.1109/LED.2026.3723903","DOIUrl":"https://doi.org/10.1109/LED.2026.3723903","url":null,"abstract":"Bio-inspired visual systems, owing to their event-driven operation, rapid response, and low-power processing capabilities, have emerged as promising candidates for next-generation efficient visual processing architectures. However, existing bio-inspired visual systems frequently employ rate coding, which necessitates a large number of spikes, thereby leading to high energy consumption and latency. This work demonstrates a compact single-spiking visual neuron and system based on a VO2 memristor. With a feedback-controlled leaky integrate-and-fire circuit, the neuron emits only one spike under each input stimulus. By further introducing an optical sensor into the input path, illuminance can be directly encoded into spike timing. In simulations, the resulting single-spike visual system achieves 92.88% accuracy on the Modified National Institute of Standards and Technology (MNIST) classification task, while reducing the average energy consumption and average decision time by <inline-formula> <tex-math>$12.2times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.96times $ </tex-math></inline-formula>, respectively, compared with rate coding. These results indicate that the proposed neuron and system provide a new route toward efficient neuromorphic visual systems.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2023-2026"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Changes to the Editorial Board 编辑委员会的变动

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3707710

Kelin J. Kuhn

引用次数: 0

IEEE Electron Device Letters Information for Authors IEEE电子器件通讯作者信息

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3731837

引用次数: 0