IEEE Electron Device Letters最新文献

{"title":"Double-Hump Behavior in Multilayer IGZO FETs for 3D DRAM","authors":"Tiantian Wei;Jing Liang;Xuezheng Ai;Jianqi Chen;Chao Zhao","doi":"10.1109/LED.2026.3704544","DOIUrl":"https://doi.org/10.1109/LED.2026.3704544","url":null,"abstract":"Multilayer vertical channel-all-around (CAA) field-effect transistors (FETs) with amorphous indium-gallium-zinc-oxide (IGZO) channels for high-density 3D DRAM were prepared. This innovative architecture enables a cost-effective fabrication process and improves fabrication efficiency, as transistors on all layers share a single lithography and etching step, as well as the subsequent continuous deposition of the channel layer, gate insulator layer, and gate electrode. To analyze the origin of the double-hump phenomenon in the transfer curve, a parasitic-channel model was proposed and TCAD simulations were performed. It can be concluded that the parasitic-channel IGZO grown on oxide has more oxygen vacancies compared to the main-channel IGZO grown on nitride. A higher concentration of donor oxygen vacancies generates more electrons, which causes the parasitic channel to turn on the transistor earlier than the main channel, leading to the double-hump phenomenon. When the parasitic channel is removed, the double-hump effect disappears, which has been verified by both simulation and experimental results.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1559-1562"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"600 V/1 A Enhancement-Mode β-Ga2O3 MOSFETs With Graded Doping Engineering","authors":"Hongqing Yue;Chenlu Wang;Hong Zhou;Jianghan Zhao;Yue Hao;Jincheng Zhang","doi":"10.1109/LED.2026.3701514","DOIUrl":"https://doi.org/10.1109/LED.2026.3701514","url":null,"abstract":"In this letter, we have demonstrated high performance enhancement-mode (E-mode) <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga₂O₃ recessed-gate metal-oxide-semiconductor field-effect- transistors (RG-MOSFETs) with ampere-level drain current (<inline-formula> <tex-math>${I}_{text {D}}text {)}$ </tex-math></inline-formula> and > 600 V breakdown voltage (BV) via graded channel doping engineering. With the n⁺- and n-Ga₂O₃ layers beneath the gate etched and the unintentional doped- (UID-)Ga₂O₃ preserved, the threshold voltage (<inline-formula> <tex-math>${V}_{text {TH}}text {)}$ </tex-math></inline-formula> with high uniformity of 9 V, a recorded top-gate E-mode <inline-formula> <tex-math>${I}_{text {D}}$ </tex-math></inline-formula> of 130 mA/mm and low specific on-resistance (<inline-formula> <tex-math>${R}_{text {on, {sp}}}text {)}$ </tex-math></inline-formula> of 19 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm² are all achieved for small periphery FETs. Combined with source and gate field plates (FP), the small periphery RG-MOSFET with gate-to-drain spacing (<inline-formula> <tex-math>${L}_{text {GD}}text {)}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m demonstrates a high <italic>BV</i> of <inline-formula> <tex-math>$2.46~{k}$ </tex-math></inline-formula>V, yielding a state-of-the-art power figure of merit (P-FOM) of 318 MW/cm². By scaling the gate width (<inline-formula> <tex-math>${W}_{text {ch}}text {)}$ </tex-math></inline-formula> to 20 mm, Ampere-level <inline-formula> <tex-math>${I}_{text {D}}$ </tex-math></inline-formula> with <italic>BV &gt; 600</i> V was also achieved with <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> maintained to be ~9 V, showing a high process variation immunity. Given the significant potential of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga₂O₃ MOSFETs in power devices, such E-mode high-current and high-voltage results verify their great promises for next-generation electronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1535-1538"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Gain Hydrogen-Terminated Diamond Logic Circuits With Low Power-Consumption","authors":"Lei Ge;Siying Gao;Xuemin Zhao;Mingyang Wang;Yaxin Li;Runlei Zhang;Xiaohua Chen;Saibin Han;Yingnan Wang;Yan Peng;Zai-xing Yang;Jisheng Han;Mingsheng Xu;Xiangang Xu","doi":"10.1109/LED.2026.3701759","DOIUrl":"https://doi.org/10.1109/LED.2026.3701759","url":null,"abstract":"Hydrogen-terminated diamond field effect transistors (FETs) are typically depletion-mode devices, which limits their application in low-power-consumption logic circuits. Here, high-performance inverters and ring oscillators have been demonstrated by using normally-off Al/BaF₂/H-diamond FETs. The adoption of enhancement-mode transistors enables the realization of low-static-power logic circuits by employing diamond FETs with different channel lengths as load and driver devices. The peak gain of the inverter increases from −100 V/V to −460 V/V as the supply voltage ranges from −1 V to −5 V with a static power consumption low to ~1 pW, marking the highest gain reported for diamond-based inverters. Furthermore, a five-stage ring oscillator operates at 58.8 kHz with a stage delay of <inline-formula> <tex-math>$1.7~mu $ </tex-math></inline-formula>s under a supply voltage of −3 V, marking the first successful implementation of a diamond-based ring oscillator. These results highlight the great potential of diamond technology for high-speed power integrated circuit applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1655-1658"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11560869","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Voltage GaN Polarization Superjunction HEMT Resisting Dynamic On-Resistance Degradation Through the 2DHG Shielding of the Surface Charge Trapping","authors":"Dequ Gu;Huaize Liu;Hui Guo;Pengfei Shao;Ruiling Gong;Guang Qiao;Yugang Zhou;Bin Liu;Hai Lu;Rong Zhang;Youdou Zheng;Dunjun Chen","doi":"10.1109/LED.2026.3698956","DOIUrl":"https://doi.org/10.1109/LED.2026.3698956","url":null,"abstract":"In this letter, we report a high-voltage GaN polarization superjunction (PSJ) high-electron-mobility transistor (HEMT) with ultralow dynamic on-resistance (<inline-formula> <tex-math>${R}_{text {ON}}text {)}$ </tex-math></inline-formula> degradation. Compared with the Ref-HEMT (without PSJ structure), the PSJ-HEMT exhibits much higher breakdown voltage, which exceeds 4200 V with a gate-to-drain distance of <inline-formula> <tex-math>$30~mu $ </tex-math></inline-formula>m, corresponding to a breakdown field of 1.4 MV/cm. More importantly, PSJ-HEMT shows outstanding resistance to dynamic <inline-formula> <tex-math>${R}_{text {ON}}$ </tex-math></inline-formula> degradation, maintaining an ultralow dynamictostatic <inline-formula> <tex-math>${R}_{text {ON}}$ </tex-math></inline-formula> ratio of 1.59 after a 10ms, 1500V offstate stress. These improvements are further analyzed by electric-field simulations and temperature-dependent stress measurements, being attributed to the flattening of the lateral electric field and the screening of surface charge trapping by the 2DHG in the PSJ structure. This work demonstrates the strong potential of PSJ-HEMTs for future power applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1531-1534"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved Energy Resolution in Amorphous Selenium X-Ray Detectors via Unipolar Charge Sensing","authors":"Ahmet Camlica;Yagiz Mart;Peter M. Levine;Denny L. Lee;Karim S. Karim","doi":"10.1109/LED.2026.3707424","DOIUrl":"https://doi.org/10.1109/LED.2026.3707424","url":null,"abstract":"This letter presents a unipolar charge-sensing amorphous selenium (a-Se) detector architecture addressing spectral limitations of conventional planar designs, where incomplete, depth-dependent electron collection leads to photopeak broadening and low-energy tailing. Detectors with <inline-formula> <tex-math>$20~upmu text {m}$ </tex-math></inline-formula> pixel pitch were fabricated and characterized using pulse-height spectroscopy. Transient measurements indicate that unipolar sensing effectively suppresses the influence of slow electron transport on the detector response, reducing rise time from 0.6–<inline-formula> <tex-math>$22.4~upmu text {s}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$150~pm ~11$ </tex-math></inline-formula> ns. The proposed architecture achieves an energy resolution of 8.3 keV FWHM at 59.5 keV with suppressed spectral tailing, demonstrating a scalable pathway toward high-performance a-Se photon-counting detectors for applications such as spectral mammography.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1635-1638"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Electron Device Letters Publication Information","authors":"","doi":"10.1109/LED.2026.3709231","DOIUrl":"https://doi.org/10.1109/LED.2026.3709231","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"C2-C2"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11626929","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Ballistic Injection in IGZO GAA VFET With Scaled Source/Drain Extension and Its Impact on On-Current Enhancement","authors":"Liankai Zheng;Ziheng Wang;Zhiyu Lin;Mengwei Si","doi":"10.1109/LED.2026.3706796","DOIUrl":"https://doi.org/10.1109/LED.2026.3706796","url":null,"abstract":"In this work, the impact of source/drain (S/D) extension scaling on the performance of indium-gallium-zinc oxide (IGZO) gate-all-around (GAA) vertical field-effect transistors (VFETs) is systematically studied both theoretically and experimentally. The electron transport at the S/D extension is investigated by drift-diffusion (DD) simulation and ballistic injection simulation. It is observed that the I-V characteristics at high V_DS of IGZO GAA VFET with scaled S/D extension deviate significantly from the velocity saturation model due to the electron velocity overshoot at the S/D extension region. A ballistic injection model is introduced that can well explain the experimental I-V characteristics. It is found that the S extension scaling, rather than the D extension scaling, is more effective for on-current (I<inline-formula> <tex-math>${}_{text {on}}text {)}$ </tex-math></inline-formula> enhancement. By S extension scaling (down to 5 nm), the I_on enhancement is demonstrated experimentally, showing a high I_on of <inline-formula> <tex-math>$569~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m (V<inline-formula> <tex-math>${}_{text {D}} =2.2$ </tex-math></inline-formula> V).","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1587-1590"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Seed-Iteration-Epitaxy Technique Achieving High-Mobility Poly-Si Channel for BEOL-Compatible Three-Dimensional Integration","authors":"Jinbiao Liu;Xianglie Sun;Zhuo Chen;Jianfeng Gao;Xiaobin He;Wenjuan Xiong;Chenchen Zhang;Junfeng Li;Chao Zhao;Shujuan Mao;Jun Luo","doi":"10.1109/LED.2026.3705796","DOIUrl":"https://doi.org/10.1109/LED.2026.3705796","url":null,"abstract":"In this work, we demonstrate a back-end-of-line (BEOL)-compatible seed-iteration-epitaxy (SIE) technique, achieving high-quality Si crystallization with a grain size of <inline-formula> <tex-math>$1.83~mu $ </tex-math></inline-formula>m and an integrity factor of 0.9. The SIE technique consists of two sequential steps: (1) grain-filter (GF)-based seed preparation to form high-quality poly-Si seeds and (2) seed-assisted crystallization, where liquid phase epitaxy (LPE)-like growth occurs using the underlying seeds as templates. At the device level, by utilizing the SIE approach, excellent electrical performance is achieved for NMOS, showing ON-OFF current ratio (<inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}text {)}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$2.1times 10^{{7}}$ </tex-math></inline-formula>, subthreshold swing (<italic>SS</i>) of 82.8 mV/dec, and field-effect mobility (<inline-formula> <tex-math>$mu _{text {FE}}text {)}$ </tex-math></inline-formula> of 605 cm²/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s. This approach provides a promising pathway for integrating high-mobility channel materials with potential relevance to future three-dimensional integration and memory applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1627-1630"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Changes to the Editorial Board","authors":"Kelin J. Kuhn","doi":"10.1109/LED.2026.3707329","DOIUrl":"https://doi.org/10.1109/LED.2026.3707329","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1499-1499"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11627133","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On-Chip Integrated CsPbBr3 Sheet-Cathode Vacuum Nanodiode for Direct Electron Irradiation Detection","authors":"Xiaohang Long;Yang Chen;Yifeng Huang;Zairan Liu;Guichen Song;Jun Chen;Shaozhi Deng;Fei Liu;Juncong She","doi":"10.1109/LED.2026.3699323","DOIUrl":"https://doi.org/10.1109/LED.2026.3699323","url":null,"abstract":"We demonstrate an on-chip integrated vacuum nanodiode with a CsPbBr₃ sheet-cathode for direct electron detection. Under 5 keV electron irradiation at a beam current of 100 pA, the device achieves an on/off ratio of 248 at a cathode-anode bias of 15 V, enabling high contrast detection due to the low dark current of ~100 pA. At a bias of 23.5 V, the detection efficiency reaches 141%, exceeding the theoretical gain from impact ionization and thus enabling high sensitivity detection. This work extends vacuum nanodiodes to direct electron detection. The high responsivity and on-chip integrability make the device promising for detector arrays in high-throughput multi-beam scanning electron microscopy.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1647-1650"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}