IEEE Electron Device Letters最新文献_第3页

Quantifying the Contact Resistance Components in Oxide Thin-Film Transistor 氧化物薄膜晶体管中接触电阻分量的量化

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-04 DOI: 10.1109/LED.2026.3719158

Wenhui Wang;Zelin Yuan;Haoran Peng;Panpan Zhang;Yida Li

{"title":"Quantifying the Contact Resistance Components in Oxide Thin-Film Transistor","authors":"Wenhui Wang;Zelin Yuan;Haoran Peng;Panpan Zhang;Yida Li","doi":"10.1109/LED.2026.3719158","DOIUrl":"https://doi.org/10.1109/LED.2026.3719158","url":null,"abstract":"Understanding the contact resistance (<inline-formula> <tex-math>${R}_{C}text {)}$ </tex-math></inline-formula> of back-end-of-line (BEOL) compatible oxide thin-film transistors (TFTs) is critical for drive current optimization especially in advanced technology node. Here, we elucidate the contributions of <inline-formula> <tex-math>${R}_{C}$ </tex-math></inline-formula> in an indium–gallium–zinc oxide (IGZO) TFT by integrating the transfer length method (TLM) and contact-end-resistance (CER) model, supported by physical and material characterization of the TFT, where <inline-formula> <tex-math>${R}_{C}$ </tex-math></inline-formula> is divided into the Schottky barrier resistance (<inline-formula> <tex-math>${R}_{textit {SC}}text {)}$ </tex-math></inline-formula>, the effective interlayer resistance (<inline-formula> <tex-math>${R}_{textit {Int}}text {)}$ </tex-math></inline-formula>, and the resistance of IGZO beneath the contacts (<inline-formula> <tex-math>${R}_{textit {IGZO}}text {)}$ </tex-math></inline-formula>. Using our fabricated IGZO TFT as a test vehicle, we show that the <inline-formula> <tex-math>${R}_{textit {IGZO}}$ </tex-math></inline-formula> represents around two-thirds of the total <inline-formula> <tex-math>${R}_{C}$ </tex-math></inline-formula> and a significant one-third contributed by the interfacial contact layer, with a negligible <inline-formula> <tex-math>${R}_{textit {SC}}$ </tex-math></inline-formula>. By decomposing the <inline-formula> <tex-math>${R}_{C}$ </tex-math></inline-formula> components, they can be separately addressed for device optimization, thus guiding device architecture or process design for future monolithic three-dimensional chip.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2055-2058"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Density 3-D-DRAM Architecture With Folded Capacitor for Sub-10-nm Scaling 采用折叠电容的高密度3-D-DRAM架构

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-07-21 DOI: 10.1109/LED.2026.3715518

Munhyeon Kim;Woohyun Lee;Junhyeok Kim;Jae-Joon Kim

{"title":"High-Density 3-D-DRAM Architecture With Folded Capacitor for Sub-10-nm Scaling","authors":"Munhyeon Kim;Woohyun Lee;Junhyeok Kim;Jae-Joon Kim","doi":"10.1109/LED.2026.3715518","DOIUrl":"https://doi.org/10.1109/LED.2026.3715518","url":null,"abstract":"In this letter, a novel 3D-DRAM process architecture based on a folded capacitor is proposed to enhance the bit-cell density of 3D-DRAM, one of the most promising candidates for sub-10 nm DRAM technology nodes. This work comprehensively introduces a manufacturable solution that includes bit-cell layout design, structural configuration, and a process integration scheme, ensuring design-to-fab applicability. To conduct a rigorous evaluation, structural characteristics of the proposed memory cell are precisely calibrated through Technology Computer-Aided Design (TCAD) simulations and BSIM-CMG modeling, using silicon-verified hardware data. As a result, the proposed cell exceeds a <inline-formula> <tex-math>${3}.{3}times $ </tex-math></inline-formula> increase in storage capacitance (<inline-formula> <tex-math>${C}_{text {S}}$ </tex-math></inline-formula>) within the same footprint compared to state-of-the-art 3D-DRAM with horizontal capacitor. Moreover, it secures over a 28% improvement in bit-cell density within the operational margin that guarantees reliable memory performance, highlighting its potential as a next-generation DRAM architecture.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2003-2006"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Emittance-Limited Beam Radius of Pencil Beams in Terahertz Vacuum Electron Devices 太赫兹真空电子器件中铅笔束的发射半径限制

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-03 DOI: 10.1109/LED.2026.3719330

Duo Xu;Shaomeng Wang;Zhanliang Wang;Zhigang Lu;Zhaoyun Duan;Yubin Gong

引用次数: 0

Reliable Bi-Layer HfO2/Zr-Doped ZnO Memristive Synaptic Devices 可靠的双层HfO2/ zr掺杂ZnO忆阻突触器件

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-11 DOI: 10.1109/LED.2026.3722740

Dong Min Kim;Yu Bin Kim;Sung Ho Kim;Shivam Kumar Gautam;Hi-Deok Lee

{"title":"Reliable Bi-Layer HfO2/Zr-Doped ZnO Memristive Synaptic Devices","authors":"Dong Min Kim;Yu Bin Kim;Sung Ho Kim;Shivam Kumar Gautam;Hi-Deok Lee","doi":"10.1109/LED.2026.3722740","DOIUrl":"https://doi.org/10.1109/LED.2026.3722740","url":null,"abstract":"Oxide-based memristive synaptic devices are promising hardware elements for neuromorphic computing, but stochastic resistive switching caused by uncontrolled defect distributions and localized conductive paths remains a critical challenge. Here, we demonstrate Zr-doped ZnO memristive synaptic devices fabricated using an atomic layer deposition (ALD) super-cycle process to regulate both defect states and surface morphology. X-ray photoelectron spectroscopy revealed a decrease in the VO-related O 1s component from 34.9% to 23.2%, while atomic force microscopy showed a reduction in RMS surface roughness from 0.7532 to 0.2603 nm with less distinguishable surface-grain features. These results suggest that Zr incorporation suppresses VO-related defects and reduces grain-boundary-assisted localized conduction. Compared with the undoped device, the Zr-doped device exhibited improved switching uniformity, reduced resistance-state variation, stable pulse endurance, and retention for over <inline-formula> <tex-math>${10}^{{4}}$ </tex-math></inline-formula> s at 25, 50, and <inline-formula> <tex-math>$75~^{circ }$ </tex-math></inline-formula>C. The regulated defect distribution and surface morphology enabled gradual and reproducible conductance modulation during long-term potentiation and depression, resulting in improved synaptic linearity. Neural network simulations using experimentally extracted LTP/LTD nonlinearity parameters further demonstrated enhanced recognition accuracy in ANN and CNN classification tasks.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2115-2118"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

4-Transistor IGZO Ternary Content Addressable Memory Enabling Large-Scale Array Integration for In-Memory Computing 4晶体管IGZO三元内容可寻址存储器，实现内存计算的大规模阵列集成

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-21 DOI: 10.1109/LED.2026.3725692

Taewon Seo;Taejun Ha;Seunghyun Son;Sunmean Kim;Yoonyoung Chung

{"title":"4-Transistor IGZO Ternary Content Addressable Memory Enabling Large-Scale Array Integration for In-Memory Computing","authors":"Taewon Seo;Taejun Ha;Seunghyun Son;Sunmean Kim;Yoonyoung Chung","doi":"10.1109/LED.2026.3725692","DOIUrl":"https://doi.org/10.1109/LED.2026.3725692","url":null,"abstract":"We report a 4-transistor (4T) Ternary Content Addressable Memory (TCAM) that significantly reduces the physical footprint by employing dual-gate IGZO transistors. High-density TCAMs are essential components for memory augmented neural networks and advanced computing systems; however, the large physical footprint remains a significant limitation in conventional designs. The proposed TCAM unit cell adopts a simplified structure, reducing the transistor count to four, which is substantially lower than previous SRAM-based (16T) and oxide semiconductor-based (6T) counterparts. Moreover, connecting the search line directly to the gate electrode effectively mitigates IR drop, enhancing the design’s suitability for large-scale memory applications. Experimental results validate the proposed design, demonstrating accurate Hamming distance computations (155.9 nA/bit), high endurance (<inline-formula> <tex-math>$gt$ </tex-math></inline-formula><inline-formula> <tex-math>$10^{{10}}$ </tex-math></inline-formula> cycles), and fast operation with 350 ps search latency and 220 ns write time.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2015-2018"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experimental Demonstration of Nonlinear Photoconductive Gain in N-Doped β-Ga2O3 Devices 掺n β-Ga2O3器件非线性光导增益的实验证明

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-10 DOI: 10.1109/LED.2026.3721486

Vikash K. Jangir;Sudip K. Mazumder

{"title":"Experimental Demonstration of Nonlinear Photoconductive Gain in N-Doped β-Ga2O3 Devices","authors":"Vikash K. Jangir;Sudip K. Mazumder","doi":"10.1109/LED.2026.3721486","DOIUrl":"https://doi.org/10.1109/LED.2026.3721486","url":null,"abstract":"In this Letter, we report field-tunable nonlinear photoconductive gain in vertical <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 photoconductive detectors under sub-bandgap visible-light excitation. Devices fabricated on a 5.6-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick nitrogen-doped semi-insulating <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 epilayer grown on a conductive Sn-doped substrate were characterized under 445-nm continuous-wave illumination. A distinct transition from linear to nonlinear photoconductive behavior was observed near 325–350 V, corresponding to a nominal average threshold electric field of <bold>~ 0.58-0.63 MV/cm, with the photocurrent subsequently increasing by more than 20-fold and reaching approximately <inline-formula> <tex-math>$475~mu $ </tex-math></inline-formula>A at 435–445 V. Complementary TCAD simulations reveal high local electric fields and a rapid increase in the impact-ionization generation rate at high bias, suggesting a possible contribution from impact-ionization-assisted carrier multiplication to the observed gain.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2083-2086"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Changes to the Editorial Board 编辑委员会的变动

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3707713

Kelin J. Kuhn

引用次数: 0

Changes to the Editorial Board 编辑委员会的变动

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3707711

Kelin J. Kuhn

引用次数: 0

IEEE Transactions on Electron Devices Table of Contents IEEE电子器件汇刊目录

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3731839

引用次数: 0

Performance Enhancement of IGZO Thin-Film Transistors by Ultrathin Te Back-Channel Heterojunction Capping 超薄Te背道异质结封盖提高IGZO薄膜晶体管性能

IF 4.6 2区工程技术

IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-02 DOI: 10.1109/LED.2026.3724062

Kai-Jhih Gan;Chong Ma;Zefu Zhao;Jialong Xiang;Tiaoyang Li;Shaohao Wang;Dun-Bao Ruan

{"title":"Performance Enhancement of IGZO Thin-Film Transistors by Ultrathin Te Back-Channel Heterojunction Capping","authors":"Kai-Jhih Gan;Chong Ma;Zefu Zhao;Jialong Xiang;Tiaoyang Li;Shaohao Wang;Dun-Bao Ruan","doi":"10.1109/LED.2026.3724062","DOIUrl":"https://doi.org/10.1109/LED.2026.3724062","url":null,"abstract":"Ultrathin p-type capping layers were introduced to modulate the back-channel surface of IGZO thin-film transistors (TFTs). Among Te, NiOx, and SnOx capping layers, the Te-capped IGZO TFT exhibits the best balanced performance, with a subthreshold swing (SS) of 67.1 mV/dec, a field-effect mobility (<inline-formula> <tex-math>$mu _{text {FE}}text {)}$ </tex-math></inline-formula> of 25.6 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, an on/off current (Ion/<inline-formula> <tex-math>$mathrm{I}_{text {off}}text {)}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>${1}.{06}times {10} ^{{9}}$ </tex-math></inline-formula>, and a threshold voltage (<inline-formula> <tex-math>$mathrm{V}_{text {TH}}text {)}$ </tex-math></inline-formula> of −0.035 V. Compared with the control device, Te capping reduces SS by 63%, enhances <inline-formula> <tex-math>$mu _{text {FE}}$ </tex-math></inline-formula> by 43%, and shifts VTH positively by 0.945 V. The Ion/Ioff ratio also increases by 49.3 times. The 2-nm Te layer therefore enables simultaneous improvement in switching steepness, carrier transport, and VTH control through back-channel modulation.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2067-2070"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0