IEEE Electron Device Letters最新文献_第3页

Comparison of Output Characteristics of Vanadium-Compensated 4H-SiC PCSS at 1064 nm and 355 nm 钒补偿4H-SiC PCSS在1064 nm和355 nm输出特性的比较

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-28 DOI: 10.1109/LED.2025.3564770

Fuyin Liu;Ripin Wang;Ting He;Bohan Li;Yuchen Liu;Muyu Yi;Langning Wang;Tao Xun

引用次数: 0

A Gate-Assisted Dual-Functional GaN p-n Diode for High-Speed Visible Light Communication 用于高速可见光通信的门辅助双功能GaN p-n二极管

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-28 DOI: 10.1109/LED.2025.3565044

Muhammad Hunain Memon;Huabin Yu;Yang Kang;Zhichong Wang;Alireza Hosseini;Yuanmin Luo;Zhixiang Gao;Dongyang Luo;Haiding Sun

{"title":"A Gate-Assisted Dual-Functional GaN p-n Diode for High-Speed Visible Light Communication","authors":"Muhammad Hunain Memon;Huabin Yu;Yang Kang;Zhichong Wang;Alireza Hosseini;Yuanmin Luo;Zhixiang Gao;Dongyang Luo;Haiding Sun","doi":"10.1109/LED.2025.3565044","DOIUrl":"https://doi.org/10.1109/LED.2025.3565044","url":null,"abstract":"Multifunctional integration is emerging as a critical focus in optical communication research, especially for visible light communication (VLC) systems. A key challenge is developing diodes capable of efficient signal modulation and sensitive detection of superimposed optoelectrical signals, essential for advanced VLC applications. In this work, we integrated a metal-oxide gate terminal (Gt) onto a GaN-based blue diode, significantly improving both emission and detection functionalities. In emitter mode, this integrated approach achieves a 162% improvement in modulation bandwidth, increasing from 98 MHz with a conventional bias-tee to 257 MHz using the Gt configuration. Further, incorporating a reflective electrode with the Gt improves the device’s performance, increasing the light output power by 37% and external quantum efficiency by 34%, resulting in a data rate increase of 14.2%, from 0.89 to 1.03 Gbps. In detector mode, the diode effectively detects high-speed superimposed optoelectrical signals, facilitating secure and efficient communication. This multifunctional diode provides enhanced modulation and detection capabilities, offering a promising platform for next-generation VLC and optical communication systems.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1163-1166"},"PeriodicalIF":4.1,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modular HfOx-RRAM for On-Demand Micromodular Electronics 模块化HfOx-RRAM按需微模块电子

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-28 DOI: 10.1109/LED.2025.3564850

Siddharth Kurup;Swagat Bhattacharya;Rebecca K. Banner;Kaifan Yue;Praveen Raj Ayyappan;Daniel Aziz;Hubert N. Elly;Kira L. Barton;Jennifer Hasler;Michael A. Filler;Eric M. Vogel

引用次数: 0

Unraveling the Influence of Temperature on Charge Dynamics in Quantum Dot Light-Emitting Diodes 揭示温度对量子点发光二极管电荷动力学的影响

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-25 DOI: 10.1109/LED.2025.3564505

Jingrui Ma;Siqi Jia;Xiangwei Qu;Kai Wang;Lei Jin;Xiao Wei Sun

引用次数: 0

Pathways for Retention Boost in Atomic Layer Etched IGZO-Based Capacitorless DRAM 原子层蚀刻igzo基无电容DRAM中提高保留率的途径

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-24 DOI: 10.1109/LED.2025.3564187

K. Izukashi;D. Matsubayashi;A. Belmonte;S. Kundu;Y. Wan;F. G. Redondo;H. Oh;A. Sharma;S. Subhechha;H. Puliyalil;A. Chasin;H. Dekkers;A. Pavel;N. Rassoul;G. S. Kar

{"title":"Pathways for Retention Boost in Atomic Layer Etched IGZO-Based Capacitorless DRAM","authors":"K. Izukashi;D. Matsubayashi;A. Belmonte;S. Kundu;Y. Wan;F. G. Redondo;H. Oh;A. Sharma;S. Subhechha;H. Puliyalil;A. Chasin;H. Dekkers;A. Pavel;N. Rassoul;G. S. Kar","doi":"10.1109/LED.2025.3564187","DOIUrl":"https://doi.org/10.1109/LED.2025.3564187","url":null,"abstract":"By adopting atomic layer etching as an active patterning technique for InGaZnO (IGZO) based thin-film transistors in a 300-mm fab, we demonstrate 40 nm gate-length two-transistors zero-capacitor (2T0C) dynamic random-access memory (DRAM) devices with retention time >200 s at <inline-formula> <tex-math>$95~^{circ }$ </tex-math></inline-formula>C. Our extensive 2T0C retention tests clarify that retention property can be boosted by 1) suppression of sidewall metal residues to be extrinsic leakage paths; 2) reduction of the subthreshold leakage by negative hold voltage optimization; 3) optimal gate oxide thickness to avoid gate leakage enhancement. Additionally, by utilizing dedicated large gate-area test devices, we successfully identify the driving mechanisms of gate leakage in write and read transistors as Poole-Frenkel emission and direct tunnelling, respectively. The devices can also achieve endurance <inline-formula> <tex-math>$gt 10^{{12}}$ </tex-math></inline-formula> cycles with write time <10> <tex-math>$95~^{circ }$ </tex-math></inline-formula>C, satisfying the requirements towards future 2T0C DRAM applications with significantly reduced refresh rate.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1111-1114"},"PeriodicalIF":4.1,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10975791","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SnO2/Perovskite Buried Interfacial Modification for Efficient and Stable Perovskite Solar Cells SnO2/钙钛矿埋藏界面改性制备高效稳定的钙钛矿太阳能电池

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-24 DOI: 10.1109/LED.2025.3563959

Qiuxu Lin;Gangjian Hu;Jizhong Jiang;Xinglu Xu;Wei Wei;Liang Shen

{"title":"SnO2/Perovskite Buried Interfacial Modification for Efficient and Stable Perovskite Solar Cells","authors":"Qiuxu Lin;Gangjian Hu;Jizhong Jiang;Xinglu Xu;Wei Wei;Liang Shen","doi":"10.1109/LED.2025.3563959","DOIUrl":"https://doi.org/10.1109/LED.2025.3563959","url":null,"abstract":"Organic-inorganic halide perovskite solar cells (PSCs) with n-i-p architectures exhibit significant potential for commercialization owing to their impressive power conversion efficiency and chemical stability. However, interfacial defects between electron transport layers (ETLs) and perovskite films present a critical challenge that significantly limits the photovoltaic performance. Here, we introduce 5-(trifluoromethyl) pyridine-2-carboxylic acid (TPCA) as a multifunctional interfacial modifier at the SnO2/perovskite buried interface. TPCA effectively passivates Sn-OH dangling bonds on the SnO2 surface while modulating surface energy to guide the crystallization of perovskite films. Through this synergistic mechanism combining chemical passivation and physical modulation, the maximum power conversion efficiency (PCE) of perovskite solar cells modified by TPCA has increased from 22.10% to 24.38%. Furthermore, unencapsulated TPCA-treated PSCs maintained 90.7% of their initial efficiency after 1,000 hours, showing superior long-term stability. This work provides a practical interface engineering approach to advance both efficiency and stability in perovskite optoelectronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1167-1170"},"PeriodicalIF":4.1,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Power CMOS Inverter Using Homogeneous Monolayer WSe₂ Channel With Polarity Control 具有极性控制的均匀单层WSe 2通道低功耗CMOS逆变器

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-24 DOI: 10.1109/LED.2025.3564164

Ching-Hao Hsu;Fa-Rong Hou;Ta-Wei Hsu;Yu-Tung Lin;Sui-An Chou;Ming-Han Chang;Li-Ya Chiu;Zheng-Da Huang;I-Chih Ni;Ang-Sheng Chou;Chih-I Wu

{"title":"Low-Power CMOS Inverter Using Homogeneous Monolayer WSe₂ Channel With Polarity Control","authors":"Ching-Hao Hsu;Fa-Rong Hou;Ta-Wei Hsu;Yu-Tung Lin;Sui-An Chou;Ming-Han Chang;Li-Ya Chiu;Zheng-Da Huang;I-Chih Ni;Ang-Sheng Chou;Chih-I Wu","doi":"10.1109/LED.2025.3564164","DOIUrl":"https://doi.org/10.1109/LED.2025.3564164","url":null,"abstract":"While performance metrics of innovative technology-nodes continue to improve rapidly, energy efficiency has not kept pace. In this work, we successfully constructed a homogeneous CMOS inverter using monolayer tungsten diselenide (WSe2, a promising candidate can maintain good mobility at atomic-level thickness and offers better resistance to short-channel effects. Through different contact engineering and passivation doping approaches, the polarity of WSe2 could be effectively tailored. These module improvements are helpful to investigate the impact on threshold voltage of several critical process steps and match performance of both n and p-type field-effect transistors with low effective oxide thickness back-gate dielectrics in enhancement-mode operation. In addition, the inverters demonstrate superior performance at a relevant supply voltage (VDD) of 1.5 V: voltage gain exceeding 10 V/V, noise margin over 80%, picowatt-range static-power consumption, and near-ideal switching voltage of half-VDD. Reaching these numbers simultaneously opens up the possibilities for future-generation applications of two-dimensional material-based electronic components.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1231-1234"},"PeriodicalIF":4.1,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Optoelectronic Integrated Device Featuring Pixelated Array Thin-Film for Direct Spectral Conversion 用于直接光谱转换的像素化阵列薄膜光电集成器件

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-24 DOI: 10.1109/LED.2025.3564038

Yahui Su;Shanjing Liu;Xingchen Han;Peixuan Song;Peiran Du;Hui Wang;Xiaofang Wang;Lin Ma;Hongkun Cai;Jian Ni;Jianjun Zhang;Juan Li

{"title":"An Optoelectronic Integrated Device Featuring Pixelated Array Thin-Film for Direct Spectral Conversion","authors":"Yahui Su;Shanjing Liu;Xingchen Han;Peixuan Song;Peiran Du;Hui Wang;Xiaofang Wang;Lin Ma;Hongkun Cai;Jian Ni;Jianjun Zhang;Juan Li","doi":"10.1109/LED.2025.3564038","DOIUrl":"https://doi.org/10.1109/LED.2025.3564038","url":null,"abstract":"Optoelectronic hybrid integration technology (OHIT) is poised to meet the escalating requirements for direct spectral signal conversion in optical communication systems, particularly in the context of the big data era where photons are the medium of choice. This work presents the design and fabrication of an optoelectronic integrated device featuring pixelated array thin-film for direct spectral conversion integrating a photovoltaic (PV) component and an organic light-emitting diode (OLED) component, spanning an area of 174.2 cm2, making it particularly suitable for large-scale deployment in various practical scenarios. An anti-solvent spraying technique and a mechanical scribing method are employed to ensure the crystallization uniformity and module structural optimization for large-area PV device array, respectively. An ultra-thin Ag barrier layer is integrated into charge generation layer (CGL) of the tandem top-emission OLED (tTE-OLED) to enhance the optical-to-optical conversion efficiency. The integrated device maintains a maximum EQE* of 10.43% and a luminance* of 2032.33 Cd/m2 under severely low-light conditions of 20% power of AM1.5 solar simulator. The ability of the integrated device to facilitate direct spectral conversion even under such challenging light conditions significantly broadens its potential applications, such as visible light communication, imaging.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1143-1146"},"PeriodicalIF":4.1,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New Matrix Percolation Model for Dielectric Breakdown With Nonuniform Defect Generation 具有非均匀缺陷产生的介质击穿的新矩阵渗透模型

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-24 DOI: 10.1109/LED.2025.3563934

Chu Yan;Yi Zhao

引用次数: 0

A Novel 1T-APSUsing 22nm FD-SOI Technology With Record High Tunable Sensitivity Range 采用22nm FD-SOI技术的新型1t - apsu，具有创纪录的高可调灵敏度范围

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-24 DOI: 10.1109/LED.2025.3563988

Hui Xie;Zehua Wang;Rongshan He;Haihua Wang;Jingya Cao;Peng Zhou;Xiao-Lan Tang;Yu-Long Jiang;Yong Xu;Jing Wan

引用次数: 0