IEEE Electron Device Letters最新文献_第4页

1.4-kV Irradiation-Hardened β-Ga₂O₃ Heterojunction Barrier Schottky Diode Under 10⁷ ions/cm² Fluence and 82.1 MeV⋅cm²/mg LET Environments 在10⁷ions/cm²和82.1 MeV⋅cm²/mg LET环境下，1.4 kv辐照硬化β-Ga₂O₃异质结势垒肖特基二极管

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-24 DOI: 10.1109/LED.2025.3553579

Na Sun;Zhengliang Zhang;Feng Zhou;Tianqi Wang;Fang-Fang Ren;Shulin Gu;Hai Lu;Rong Zhang;Jiandong Ye

{"title":"1.4-kV Irradiation-Hardened β-Ga₂O₃ Heterojunction Barrier Schottky Diode Under 10⁷ ions/cm² Fluence and 82.1 MeV⋅cm²/mg LET Environments","authors":"Na Sun;Zhengliang Zhang;Feng Zhou;Tianqi Wang;Fang-Fang Ren;Shulin Gu;Hai Lu;Rong Zhang;Jiandong Ye","doi":"10.1109/LED.2025.3553579","DOIUrl":"https://doi.org/10.1109/LED.2025.3553579","url":null,"abstract":"Single event burnout (SEB) caused by heavy ion irradiation in space environments poses a significant threat to aerospace power electronic devices. This work demonstrates irradiation-hardened <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 heterojunction barrier Schottky (HJBS) diodes with exceptional SEB capability. The device design incorporates micron-scale deep trenches filled by p-type nickel oxide (NiO) and high-k BaTiO3 field-plate (FP) edge termination. This architecture efficiently extracts radiation-induced positive charges (holes) during single-event irradiation through the trenched-embedded Ni/p-NiO with low Ohmic contact resistance, significantly alleviating charge aggregation while minimizing non-uniform field distributions through strategically engineered charge drainage pathways. As a result, the HJBS device achieves a SEB voltage exceeding 1.4 kV and a SEB degradation rate of only 9.6%. This is the first demonstration of kilovolt-class radiation-hardened diodes, and its performance metrics are the best reported among SiC, GaN, Ga2O3 and Si power diodes to date. This work underscores the great potential of Ga2O3 power diodes for irradiation power applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"813-816"},"PeriodicalIF":4.1,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

E-Mode Vertical β-Ga2O3 (010) U-Trench MOSFETs With In-Situ Mg-Doped Current Blocking Layers 具有原位掺镁阻流层的e模垂直β-Ga2O3 (010) u型沟mosfet

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-24 DOI: 10.1109/LED.2025.3554401

Sudipto Saha;Walid Amir;Jiawei Liu;Lingyu Meng;Dongsu Yu;Hongping Zhao;Uttam Singisetti

{"title":"E-Mode Vertical β-Ga2O3 (010) U-Trench MOSFETs With In-Situ Mg-Doped Current Blocking Layers","authors":"Sudipto Saha;Walid Amir;Jiawei Liu;Lingyu Meng;Dongsu Yu;Hongping Zhao;Uttam Singisetti","doi":"10.1109/LED.2025.3554401","DOIUrl":"https://doi.org/10.1109/LED.2025.3554401","url":null,"abstract":"This work presents the fabrication and performance analysis of a novel enhancement-mode (E-mode) vertical <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 (010) U-trench MOSFET featuring an in-situ Mg-doped current blocking layer (CBL) for high-power applications. Utilizing metal-organic chemical vapor deposition (MOCVD), we achieved precise Mg doping of <inline-formula> <tex-math>$1.3times 10^{{19}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{{a}-{3}}$ </tex-math></inline-formula> within the CBL to enhance current blocking capability while maintaining a robust threshold voltage of 5 V and a low on-state resistance of 5 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>.cm2. The device achieved an on-current of 1.56 kA/cm2 at V<inline-formula> <tex-math>${}_{textit {GS}} =20$ </tex-math></inline-formula> V and V<inline-formula> <tex-math>${}_{textit {DS}} =40$ </tex-math></inline-formula> V. The fabricated devices demonstrate a peak breakdown voltage of 101 V with an average breakdown field strength of up to 1.68 MV.cm<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>. The calculated power device Figure of Merit is 2 MW.cm<inline-formula> <tex-math>${}^{-{2}}$ </tex-math></inline-formula>.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"725-728"},"PeriodicalIF":4.1,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10938228","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing FeFET Memory Reliability via Switching Mechanism Control by Compositionally Gradient-Stacked Hf1-xZrxO2 Films 梯度堆叠ff1 - xzrxo2薄膜开关机制控制提高ffet记忆可靠性

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-21 DOI: 10.1109/LED.2025.3553762

Sheng-Yen Zheng;Wei-Ning Kao;Yung-Hsien Wu

引用次数: 0

Ternary Content Addressable Memory With Ferroelectric Non-Volatile Capacitor 铁电非易失性电容三元内容可寻址存储器

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-21 DOI: 10.1109/LED.2025.3553473

Omkar Phadke;Po-Kai Hsu;Yuan-Chun Luo;Janak Sharda;Vaidehi Garg;James Read;Junmo Lee;Halid Mulaosmanovic;Stefan Dünkel;Sven Beyer;Shimeng Yu

{"title":"Ternary Content Addressable Memory With Ferroelectric Non-Volatile Capacitor","authors":"Omkar Phadke;Po-Kai Hsu;Yuan-Chun Luo;Janak Sharda;Vaidehi Garg;James Read;Junmo Lee;Halid Mulaosmanovic;Stefan Dünkel;Sven Beyer;Shimeng Yu","doi":"10.1109/LED.2025.3553473","DOIUrl":"https://doi.org/10.1109/LED.2025.3553473","url":null,"abstract":"In this letter, a ferroelectric field effect transistor (FeFET)-based charge-domain ternary content addressable memory (TCAM) is experimentally demonstrated for in-memory search. Specifically, foundry based FeFETs are configured in non-volatile capacitor (nvCAP) mode for charge-domain computation. A single TCAM cell consisting of 2 nvCAPs (i.e. two FeFETs) is used to perform the Store: bit ‘0’, ‘1’, ‘X’ and Search: bit ‘0’, ‘1’, ‘X’ operations. Further, SPICE simulations are performed to evaluate the feasibility of a scaled nvCAP device in a large TCAM array. The low C<inline-formula> <tex-math>${}_{mathbf {textit {ON}}}$ </tex-math></inline-formula>/C<inline-formula> <tex-math>${}_{mathbf {textit {OFF}}}$ </tex-math></inline-formula> ratio of a scaled device can lead to false-positive matchings, which can be countered by introducing a dummy column and input dependent charge cancellation. Finally, the charge-domain nvCAP TCAM is benchmarked against other proposed candidates, showing a <inline-formula> <tex-math>$sim 1.5times $ </tex-math></inline-formula> improvement in energy efficiency over FeFET based current domain TCAM, and a <inline-formula> <tex-math>$sim 3.3times $ </tex-math></inline-formula> improvement compared to resistive random access memory (RRAM) based TCAM.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"872-875"},"PeriodicalIF":4.1,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Linear Tuning of Positive Threshold Voltage in IGZO Thin-Film Transistors via Gate Dielectric Stack Engineering 基于栅极介电堆工程的IGZO薄膜晶体管正阈值电压线性调谐

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-21 DOI: 10.1109/LED.2025.3553826

Gangping Yan;Yanyu Yang;Lu Tai;Yuting Chen;Xueli Ma;Jinjuan Xiang;Gaobo Xu;Guilei Wang;Huaxiang Yin;Chao Zhao

{"title":"Linear Tuning of Positive Threshold Voltage in IGZO Thin-Film Transistors via Gate Dielectric Stack Engineering","authors":"Gangping Yan;Yanyu Yang;Lu Tai;Yuting Chen;Xueli Ma;Jinjuan Xiang;Gaobo Xu;Guilei Wang;Huaxiang Yin;Chao Zhao","doi":"10.1109/LED.2025.3553826","DOIUrl":"https://doi.org/10.1109/LED.2025.3553826","url":null,"abstract":"The positive threshold voltage (VTH) tuning in InGaZnO (IGZO) thin-film transistors (TFTs) has become an urgent issue. In this work, the effect of different ultrathin gate dielectric interlayers (ILs) inserted between the high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> HfO2 and IGZO is investigated based on the pristine VTH of +0.064 V optimized by IGZO sputtering and post-annealing. By specifically combining varying HfO2 thicknesses and IL types, this initial VTH is linearly modulated to +0.528 V in IGZO devices without noticeable sub-threshold swing (SS) and mobility degradation. Attributed to the dipole and fixed charge modulation at the interface, the devices with 7-nm HfO2 and 2-nm SiO2 IL exhibit optimal results, including the most positive VTH, a decent mobility of 12 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, a well-maintained SS of 84.7 mV/dec, and promoted positive and negative bias stress (PBS/NBS) stability. This VTH modulation technique provides useful guidance for 3D integration such as IGZO 3D-DRAM with high performance.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"781-784"},"PeriodicalIF":4.1,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Industrially Fabricated Single-Electron Quantum Dots in Si/Si—Ge Heterostructures 工业制造的Si/Si - ge异质结构单电子量子点

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-21 DOI: 10.1109/LED.2025.3553672

Till Huckemann;Pascal Muster;Wolfram Langheinrich;Varvara Brackmann;Michael Friedrich;Nikola D. Komerički;Laura K. Diebel;Verena Stieß;Dominique Bougeard;Yuji Yamamoto;Felix Reichmann;Marvin H. Zoellner;Claus Dahl;Lars R. Schreiber;Hendrik Bluhm

{"title":"Industrially Fabricated Single-Electron Quantum Dots in Si/Si—Ge Heterostructures","authors":"Till Huckemann;Pascal Muster;Wolfram Langheinrich;Varvara Brackmann;Michael Friedrich;Nikola D. Komerički;Laura K. Diebel;Verena Stieß;Dominique Bougeard;Yuji Yamamoto;Felix Reichmann;Marvin H. Zoellner;Claus Dahl;Lars R. Schreiber;Hendrik Bluhm","doi":"10.1109/LED.2025.3553672","DOIUrl":"https://doi.org/10.1109/LED.2025.3553672","url":null,"abstract":"This letter reports the compatibility of heterostructure-based spin qubit devices with industrial CMOS technology. It features Si/Si-Ge quantum dot devices fabricated using Infineon’s 200mm production line within a restricted thermal budget. The devices exhibit state-of-the-art charge sensing, charge noise and valley splitting characteristics, showing that industrial fabrication is not harming the heterostructure quality. These measured parameters are all correlated to spin qubit coherence and qubit gate fidelity. We describe the single electron device layout, design and its fabrication process using electron beam lithography. The incorporated standard 90nm back-end of line flow for gate-layer independent contacting and wiring can be scaled up to multiple wiring layers for scalable quantum computing architectures. In addition, we present millikelvin characterization results. Our work exemplifies the potential of industrial fabrication methods to harness the inherent CMOS-compatibility of the Si/Si-Ge material system, despite being restricted to a reduced thermal budget. It paves the way for advanced quantum processor architectures with high yield and device quality.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"868-871"},"PeriodicalIF":4.1,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Asymmetric Double-Gate (ADG) Oxide Thin-Film Transistor Technology for Medium- and Small-Sized AMOLED Displays 用于中小型AMOLED显示器的非对称双栅（ADG）氧化物薄膜晶体管技术

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-21 DOI: 10.1109/LED.2025.3553527

Yuhan Zhang;Lu Chang;Lei Lu;Congwei Liao;Shengdong Zhang

引用次数: 0

Gate Stack Engineering for Top-Tier Devices in Monolithic 3D Integration Using Laser Annealing 基于激光退火的单片三维集成顶层器件的栅极堆栈工程

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-11 DOI: 10.1109/LED.2025.3549455

Youngkeun Park;Jaejoong Jeong;Semin Noh;Dongbin Kim;Heetae Kim;Sheung Hun Kim;Dae Hyun Kang;Min Ju Kim;Byung Jin Cho

{"title":"Gate Stack Engineering for Top-Tier Devices in Monolithic 3D Integration Using Laser Annealing","authors":"Youngkeun Park;Jaejoong Jeong;Semin Noh;Dongbin Kim;Heetae Kim;Sheung Hun Kim;Dae Hyun Kang;Min Ju Kim;Byung Jin Cho","doi":"10.1109/LED.2025.3549455","DOIUrl":"https://doi.org/10.1109/LED.2025.3549455","url":null,"abstract":"In this study, we propose an approach to relieve the mechanical stress in the gate stack of top-tier devices during the monolithic 3D (M3D) integration process. In the M3D process, selective laser annealing process has been actively adopted for the fabrication of top-tier devices in order to avoid possible adverse effects on pre-existing bottom-tier devices. However, the perpendicular irradiation direction during the laser annealing generates a vertical thermal gradient across the gate stack of top-tier MOS devices, resulting in unavoidable mechanical stress that is detrimental to device performance. In this work, we have demonstrated that inserting an Al2O3 layer in between the TiN gate electrode and the HfO2 gate dielectric can reduce the mechanical stress in the gate stack. This approach can reduce the residual mechanical stress in the gate stack by approximately 67%, resulting in a <inline-formula> <tex-math>$sim ~49$ </tex-math></inline-formula>% reduction in interface state density (<inline-formula> <tex-math>${D}_{{ {it}}}$ </tex-math></inline-formula>) and a <inline-formula> <tex-math>$sim ~20$ </tex-math></inline-formula>% improvement in carrier mobility.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"685-688"},"PeriodicalIF":4.1,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Highly-Sensitive Polycrystalline Diamond X-Ray Dosimeter With Hydrogen Termination Contacts 具有氢终止触点的高灵敏度多晶金刚石x射线剂量计

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-11 DOI: 10.1109/LED.2025.3549838

Kai Su;Wei Wang;Chang Liu;Jinfeng Zhang;Zeyang Ren;Yachao Zhang;Jincheng Zhang;Xiaoping Ouyang;Weimin Bao;Yue Hao

{"title":"Highly-Sensitive Polycrystalline Diamond X-Ray Dosimeter With Hydrogen Termination Contacts","authors":"Kai Su;Wei Wang;Chang Liu;Jinfeng Zhang;Zeyang Ren;Yachao Zhang;Jincheng Zhang;Xiaoping Ouyang;Weimin Bao;Yue Hao","doi":"10.1109/LED.2025.3549838","DOIUrl":"https://doi.org/10.1109/LED.2025.3549838","url":null,"abstract":"This letter reports the polycrystalline diamond (PCD) dosimeter with near ideal linearity and high sensitivity to meet the application requirements of medical X-ray dose measurement for low cost, large size, and high performance. The device is fabricated by using hydrogen termination modulation ohmic contact and high-quality materials with preferred (111) and (311) crystal orientation, large grain size and low impurity content. The linearity, specific sensitivity, and current gain obtained from experimental measurements are 0.999, <inline-formula> <tex-math>$1.482~mu $ </tex-math></inline-formula>C<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>Gy<inline-formula> <tex-math>$^{-{1}}cdot $ </tex-math></inline-formula>mm<inline-formula> <tex-math>$^{-{3}}$ </tex-math></inline-formula> and 5.76 at 300 V (1 V/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m), respectively. Furthermore, the signal-to-noise ratio that meets the requirements of International Atomic Energy Agency is greater than <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula> at 5 to 300 V, and the current fluctuations under dynamic voltage switch test condition of more than 30 cycle (2 s on-state and 1 s off-state) is only 0.241% at 200 V under dose rate of 6.184 Gy/min. This study indicates that PCD dosimeter fabricated by optimizing contact structure and material properties has a great potential for medical dose measurement.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 5","pages":"681-684"},"PeriodicalIF":4.1,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10919092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Impact of Process Steps on Nearly Ideal Subthreshold Slope in 300-mm Compatible InGaZnO TFTs 工艺步骤对300 mm兼容InGaZnO tft近理想亚阈值斜率的影响

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-03-11 DOI: 10.1109/LED.2025.3549865

Hongwei Tang;Dennis Lin;Subhali Subhechha;Adrian Chasin;Daisuke Matsubayashi;Michiel van Setten;Yiqun Wan;Harold Dekkers;Jie Li;Shruthi Subramanian;Zhuo Chen;Nouredine Rassoul;Yuchao Jiang;Jan Van Houdt;Valeri Afanas'Ev;Gouri Sankar Kar;Attilio Belmonte

引用次数: 0