IEEE Electron Device Letters最新文献_第4页

A Multifunctional Device Combining Photodetection and Neuromorphic Memory for Efficient Target Recognition 一种结合光探测和神经形态记忆的多功能目标识别装置

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-24 DOI: 10.1109/LED.2025.3563967

Bingqi Cai;Chen Wang;Kun Chen;Qingqing Sun;David Wei Zhang;Lin Chen

引用次数: 0

Vertical Channel-All-Around (CAA) IGZO FET With Recessed Source/Drain Structure to Improve Contact Characteristics 垂直通道全能（CAA） IGZO场效应管与凹源/漏结构，以改善接触特性

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-23 DOI: 10.1109/LED.2025.3563839

Chuanke Chen;Chen Gu;Yue Zhao;Xinlv Duan;Congyan Lu;Jiebin Niu;Kaiping Zhang;Yu Liu;Shengjie Zhao;Weiwei Li;Wanming Wu;Chunyu Zhang;Ke Hu;Shipeng Wang;Qingding Tong;Yinzhi Tang;Nianduan Lu;Di Geng;Ling Li

{"title":"Vertical Channel-All-Around (CAA) IGZO FET With Recessed Source/Drain Structure to Improve Contact Characteristics","authors":"Chuanke Chen;Chen Gu;Yue Zhao;Xinlv Duan;Congyan Lu;Jiebin Niu;Kaiping Zhang;Yu Liu;Shengjie Zhao;Weiwei Li;Wanming Wu;Chunyu Zhang;Ke Hu;Shipeng Wang;Qingding Tong;Yinzhi Tang;Nianduan Lu;Di Geng;Ling Li","doi":"10.1109/LED.2025.3563839","DOIUrl":"https://doi.org/10.1109/LED.2025.3563839","url":null,"abstract":"We proposed recessed source/drain(S/D) structure for vertical channel-all-around (CAA) IGZO FET to introduce contact interlayer and improve its contact characteristics. The IZO interlayer introduced between S/D and IGZO helps to reduce the contact resistance, and boosting the performance of CAA IGZO FET. The fabricated CAA IGZO FETs with 8 nm IZO interlayer show an average Ion @ V<inline-formula> <tex-math>${}_{text {th}}+1$ </tex-math></inline-formula>V of <inline-formula> <tex-math>$32.6~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, SS of 86 mV/dec, and Vth of - 0.06 V. The Schottky barrier height <inline-formula> <tex-math>${q}phi _{B}$ </tex-math></inline-formula> is extracted to be reduced from 170 meV to 65 meV by introducing the contact interlayer, which confirms the improvement of contact characteristics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1127-1130"},"PeriodicalIF":4.1,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10975041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Vertical Ultra-Wide Bandgap Al0.5Ga0.5N P-N Memory Diodes 垂直超宽带隙Al0.5Ga0.5N P-N存储二极管

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-23 DOI: 10.1109/LED.2025.3563594

Hang Chen;Shuhui Zhang;Tianpeng Yang;Tingting Mi;Xiaowen Wang;Chao Liu

引用次数: 0

InGaAlAs/InP MQW Transistor Lasers Based on Step-Ridge Waveguides 基于阶跃脊波导的InGaAlAs/InP MQW晶体管激光器

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-23 DOI: 10.1109/LED.2025.3563705

Yijia Liu;Lijun Qiao;Xin Tang;Song Liang;Mingjiang Zhang

引用次数: 0

A Mode-Localized Pressure Sensor With Dual Temperature Compensation Method 一种双温度补偿模式局域压力传感器

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-22 DOI: 10.1109/LED.2025.3563190

Jiaxin Qin;Yulan Lu;Bo Xie;Xiaoye Huo;Deyong Chen;Junbo Wang;Nan Li;Jian Chen

{"title":"A Mode-Localized Pressure Sensor With Dual Temperature Compensation Method","authors":"Jiaxin Qin;Yulan Lu;Bo Xie;Xiaoye Huo;Deyong Chen;Junbo Wang;Nan Li;Jian Chen","doi":"10.1109/LED.2025.3563190","DOIUrl":"https://doi.org/10.1109/LED.2025.3563190","url":null,"abstract":"Mode-localized pressure sensors have the advantage of high sensitivity and resolution, making them being widely studied. However, they also suffer from the influence of temperature fluctuations due to the thermal stress, but compensation method has not been explored. This study proposes a mode-localized pressure sensor with dual temperature compensation. The temperature dependence of the output signal and the compensation method is elucidated. Both passive and active methods are considered, as passive methods typically serve as the foundation for attaining an efficient active compensation outcome. Consequently, the sensor is packaged using low-stress bonding techniques, specifically Au-Si eutectic bonding. On the basis of the passive compensation, electrostatic forces are also employed to further mitigate the errors in amplitude ratio output induced by thermal stress. This approach effectively decouples the output signal from temperature. The sensor was tested from <inline-formula> <tex-math>$- 20~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$60~^{circ }$ </tex-math></inline-formula>C, and the results show the feasibility and advantages of the proposed compensation method.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1203-1206"},"PeriodicalIF":4.1,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dual-Gate Hybrid Ferroelectric Transistor Combines Photo-Switchable Logic and Memory for Encrypted Optical Communication 用于加密光通信的双栅混合铁电晶体管结合了光开关逻辑和存储器

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-22 DOI: 10.1109/LED.2025.3563268

Shasha Li;Xinyue Xu;Yong Yan

引用次数: 0

A Terahertz On-Chip Lowpass Filter Based on Spoof Surface Plasmon Polaritons 基于欺骗表面等离子激元极化的太赫兹片上低通滤波器

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-22 DOI: 10.1109/LED.2025.3563208

Kai-Da Xu;Dongxu Wang;Ying-Jiang Guo;Yiqun Liu;Pin Wen

引用次数: 0

Enhancement of Ferroelectricity in Hf0.5Zr0.5O2 via Pre-Crystallization and Interface Engineering at Ultra-Low Temperature (300 °C) Annealing 超低温（300℃）退火下Hf0.5Zr0.5O2预结晶和界面工程增强铁电性

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-22 DOI: 10.1109/LED.2025.3563376

Keyou Tong;Jing Xu;Bohan Chen;Xu Chen;Binbin Xu;Shuai Yang;Xiaolei Wang;Jun Luo

{"title":"Enhancement of Ferroelectricity in Hf0.5Zr0.5O2 via Pre-Crystallization and Interface Engineering at Ultra-Low Temperature (300 °C) Annealing","authors":"Keyou Tong;Jing Xu;Bohan Chen;Xu Chen;Binbin Xu;Shuai Yang;Xiaolei Wang;Jun Luo","doi":"10.1109/LED.2025.3563376","DOIUrl":"https://doi.org/10.1109/LED.2025.3563376","url":null,"abstract":"The interface degradation between ferroelectric film and surrounding layers limits the endurance of hafnia ferroelectric devices significantly. This letter proposes a promising TiN/TZHZT/TiN structure with TiO2/ZrO2 bi-interlayers on both sides of a sub-7 nm Hf0.5Zr0.5O2 (HZO). The TZHZT sample underwent ultra-low temperature annealing at <inline-formula> <tex-math>$300~^{circ }$ </tex-math></inline-formula>C demonstrates exceptional ferroelectric properties, i.e. significant remnant polarization (<inline-formula> <tex-math>$2{P}_{r} = 28.2~mu $ </tex-math></inline-formula>C/cm<inline-formula> <tex-math>${}^{{2}}text {)}$ </tex-math></inline-formula>, appropriate coercive field (<inline-formula> <tex-math>${E}_{c} =1.7$ </tex-math></inline-formula> MV/cm), and excellent endurance exceeding <inline-formula> <tex-math>$10^{{10}}$ </tex-math></inline-formula> cycles. Achieved results are attributed to the synergistic effects of dual interlayer engineering. Specifically, the ZrO2 interlayer promotes the growth of ferroelectric grains through the formation of seed crystals, leading to larger grain size after annealing. Meanwhile, the TiO2 interlayer enhances tensile stress and oxygen enrichment, thereby improving both <inline-formula> <tex-math>$2{P}_{r}$ </tex-math></inline-formula> and endurance. Moreover, the ZrO2 interlayer effectively compensates the deficiency of breakdown strength for TiO2 layer.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 6","pages":"928-931"},"PeriodicalIF":4.1,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144135225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing Reliability in Ferroelectric ScAlN Non-Volatile Memory With AlOₓ Layer Insertion 利用AlOₓ层插入提高铁电ScAlN非易失性存储器的可靠性

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-21 DOI: 10.1109/LED.2025.3563098

Rui Wang;Ping Wang;Haotian Ye;Ran Feng;Xifan Xu;Bingxuan An;Yuzhi Deng;Fang Liu;Bowen Sheng;Tao Wang;Xiantong Zheng;Bo Shen;Xinqiang Wang

{"title":"Enhancing Reliability in Ferroelectric ScAlN Non-Volatile Memory With AlOₓ Layer Insertion","authors":"Rui Wang;Ping Wang;Haotian Ye;Ran Feng;Xifan Xu;Bingxuan An;Yuzhi Deng;Fang Liu;Bowen Sheng;Tao Wang;Xiantong Zheng;Bo Shen;Xinqiang Wang","doi":"10.1109/LED.2025.3563098","DOIUrl":"https://doi.org/10.1109/LED.2025.3563098","url":null,"abstract":"Ferroelectric non-volatile memory (FeNVM) is gaining significant attention for its potential applications in data storage and neuromorphic computing. Among the promising materials for next-generation FeNVM, scandium aluminum nitride (ScAlN), has garnered attention due to its favorable ferroelectric properties and compatibility with existing Si and GaN semiconductor platforms, as well as CMOS technology. However, current ScAlN-based FeNVMs have been limited by a low Vb/Vsw(breakdown voltage to polarization switching voltage ratio) figure of merit (FOM) and inadequate endurance, hindering their widespread adoption. To overcome these limitations, we proposed an innovative ScAlN FeNVM architecture that incorporates an AlOx interlayer deposited via atomic layer deposition (ALD). This strategic addition significantly enhances the device’s performance, achieving a competitive Vb/Vsw FOM of 1.7 and extending the endurance to up to <inline-formula> <tex-math>$10^{{6}}$ </tex-math></inline-formula> write-erase cycles. Furthermore, our design demonstrates scalability, as evidenced by the successful integration of a 20-nm-thick ScAlN layer, which supports high-density integration in future devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1107-1110"},"PeriodicalIF":4.1,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Novel Fin-Shaped Drift SOI LDMOS Featuring Drift-All-Around Electron Accumulation Effect 具有全漂移电子积累效应的新型鳍形漂移SOI LDMOS

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-04-21 DOI: 10.1109/LED.2025.3562701

Ziye Deng;Qi Li;Lanyi Liang;Pei Li;Yulong Liu;Li Guan;Xiaosong Hu

{"title":"Novel Fin-Shaped Drift SOI LDMOS Featuring Drift-All-Around Electron Accumulation Effect","authors":"Ziye Deng;Qi Li;Lanyi Liang;Pei Li;Yulong Liu;Li Guan;Xiaosong Hu","doi":"10.1109/LED.2025.3562701","DOIUrl":"https://doi.org/10.1109/LED.2025.3562701","url":null,"abstract":"This letter proposes a novel lateral double-diffused MOSFET based on a silicon-on-insulator (SOI) structure with a drift-all-around electron accumulation layer (EAL) (DAA-LDMOS). The DAA structure incorporates a self-adaptive potential region (SAP) surrounding a fin-shaped drift region, and a control electrode atop the SAP region. The potential existing in the SAP region and buried oxide (BOX) layer is perpetually higher than in the drift region, maintaining an unwavering potential differential, which introduces a 3D fully enclosed rectangular EAL in the drift region. Moreover, a control electrode can deftly modulate the intensity of the EAL to achieve the optimal accumulation effect. Consequently, the device possesses an extremely wide current path with ultralow resistance, dramatically decreasing the specific ON-resistance R<inline-formula> <tex-math>${}_{mathbf {textit {ON},textit {sp}}}$ </tex-math></inline-formula>. The simulation results show that the <inline-formula> <tex-math>${R} _{mathbf {textit {ON},textit {sp}}}$ </tex-math></inline-formula> of the DAA-LDMOS was reduced from 12.56m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{mathbf {{2}}}$ </tex-math></inline-formula> of the conventional LDMOS (Cov. LDMOS) without accumulation effect to 0.28 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{mathbf {{2}}}$ </tex-math></inline-formula>, a reduction of 97.7% at the same breakdown voltage BV of 260 V. The figure-of-merit (FOM) of the DAA-LDMOS increased from 5.5 MW/cm<inline-formula> <tex-math>${}^{mathbf {{2}}}$ </tex-math></inline-formula> of the Cov. LDMOS to a record high of 237.7 MW/cm<inline-formula> <tex-math>${}^{mathbf {{2}}}$ </tex-math></inline-formula>, demonstrating an exceptional performance.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 7","pages":"1183-1186"},"PeriodicalIF":4.1,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0