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Reliability Improvement of Top-Gate ITO Transistors by Post-Metal Annealing at 450 °C 450°C后金属退火提高顶栅ITO晶体管的可靠性
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-12 DOI: 10.1109/LED.2026.3719443
Zhiyu Wang;Qianlan Hu;Tianyue Fu;Wenjie Zhao;Min Zeng;Shiyuan Liu;Yanqing Wu
{"title":"Reliability Improvement of Top-Gate ITO Transistors by Post-Metal Annealing at 450 °C","authors":"Zhiyu Wang;Qianlan Hu;Tianyue Fu;Wenjie Zhao;Min Zeng;Shiyuan Liu;Yanqing Wu","doi":"10.1109/LED.2026.3719443","DOIUrl":"https://doi.org/10.1109/LED.2026.3719443","url":null,"abstract":"In this letter, we present significant reliability improvement of top-gate indium-tin-oxide (ITO) transistors through an optimized two-step post-metal annealing (PMA) conducted in an oxygen atmosphere at <inline-formula> <tex-math>$450~^{text {o}}$ </tex-math></inline-formula>C. By effectively suppressing oxygen-vacancy-related traps and interfacial defects, the optimized devices achieve exceptional bias temperature stability. Under a high electric field of ±6 MV/cm at room temperature, the threshold voltage shift (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}_{text {th}}text {)}$ </tex-math></inline-formula> is minimized to 9.9 mV for positive bias temperature instability (PBTI) and 2.2 mV for negative bias temperature instability (NBTI) after 1,000 s. Furthermore, the devices maintain robust stability under simultaneous high-field of ±5 MV/cm and high-temperature of <inline-formula> <tex-math>$105~^{circ }$ </tex-math></inline-formula>C stress, exhibiting a <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<sub>th</sub> of less than 50 mV after 3,000 s. These results demonstrate superior reliability under extreme operating conditions, establishing top-gate ITO transistors as viable candidates for next-generation back-end-of-line (BEOL) compatible electronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2051-2054"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2.3-kV Vertical GaN Trench MOSFET With Variable Lateral Ion-Implanted Guard Rings 具有可变横向离子注入保护环的2.3 kv垂直GaN沟槽MOSFET
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-21 DOI: 10.1109/LED.2026.3725710
Shihao Xu;Cui Yang;Wei Mao;Chao Liu;Ming Du;Ming Xiao;Yuanyuan Xie;Yu Duan;Yuchuan Ma;Changfa Sun;Dongguo Fan;Guoliang Peng;Kai Cheng;Maojun Wang;Li Zheng;Zhihong Liu;Jincheng Zhang;Yue Hao
{"title":"2.3-kV Vertical GaN Trench MOSFET With Variable Lateral Ion-Implanted Guard Rings","authors":"Shihao Xu;Cui Yang;Wei Mao;Chao Liu;Ming Du;Ming Xiao;Yuanyuan Xie;Yu Duan;Yuchuan Ma;Changfa Sun;Dongguo Fan;Guoliang Peng;Kai Cheng;Maojun Wang;Li Zheng;Zhihong Liu;Jincheng Zhang;Yue Hao","doi":"10.1109/LED.2026.3725710","DOIUrl":"https://doi.org/10.1109/LED.2026.3725710","url":null,"abstract":"This letter presents a vertical GaN trench MOSFET featuring Variable Lateral Ion-implanted Guard Rings (VLGR) formed in a partially thinned p-GaN region to engineer the edge electric field distribution. The proposed graded termination effectively mitigates electric field crowding, enabling a breakdown voltage (<italic>BV</i>) of 2305 V—an approximately 2.7-fold improvement over the Ref-MOSFET (850 V). The fabricated device exhibits a threshold voltage (<inline-formula> <tex-math>${V}_{text {TH}}text {)}$ </tex-math></inline-formula> of 4.9 V, a specific on-resistance (<inline-formula> <tex-math>${R}_{text {on, sp}}text {)}$ </tex-math></inline-formula> of 7.2 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm<sup>2</sup>, and an on/off current ratio of <inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula>, yielding a Baliga’s figure of merit (<italic>BFOM</i>) of 738 MW/cm<sup>2</sup>. These results demonstrate an effective edge-termination strategy for extending the blocking capability of fully vertical GaN trench MOSFETs and suggest the potential of this structure for high-voltage power electronics applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2087-2090"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Changes to the Editorial Board 编辑委员会的变动
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3707712
Kelin J. Kuhn
{"title":"Changes to the Editorial Board","authors":"Kelin J. Kuhn","doi":"10.1109/LED.2026.3707712","DOIUrl":"https://doi.org/10.1109/LED.2026.3707712","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"1976-1976"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11714243","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Electron Device Letters Publication Information IEEE电子器件通讯出版信息
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-09-29 DOI: 10.1109/LED.2026.3731831
{"title":"IEEE Electron Device Letters Publication Information","authors":"","doi":"10.1109/LED.2026.3731831","DOIUrl":"https://doi.org/10.1109/LED.2026.3731831","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"C2-C2"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11714245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Performance S/D-First IGZO TFTs Integrated With p-Type Si Nanowire FETs for Complementary Logic 高性能S/D-First IGZO tft与p型Si纳米线场效应管集成，用于互补逻辑
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-24 DOI: 10.1109/LED.2026.3725781
Le Weng;Wentao Qian;Shuo Zhang;Zhinong Yu;Junzhuan Wang;Linwei Yu
{"title":"High-Performance S/D-First IGZO TFTs Integrated With p-Type Si Nanowire FETs for Complementary Logic","authors":"Le Weng;Wentao Qian;Shuo Zhang;Zhinong Yu;Junzhuan Wang;Linwei Yu","doi":"10.1109/LED.2026.3725781","DOIUrl":"https://doi.org/10.1109/LED.2026.3725781","url":null,"abstract":"High-performance complementary logic requires process-compatible n-type and p-type devices with low degradation. Here, we report the heterogeneous integration of source/drain-first (S/D-first) IGZO TFTs with in-plane solid–liquid–solid (IPSLS)-grown p-type Si nanowire (SiNW) FETs for complementary logic. The S/D-first process effectively suppresses lithography-induced channel damage, thereby enabling that the field-effect mobility of IGZO TFT increases to 31.4 cm<sup>2</sup> V<sup>-1</sup> s<sup>-1</sup>, while the subthreshold swing decreases 166 mV dec<sup>-1</sup>. Meanwhile, the p-SiNW FETs exhibit a field-effect mobility of 54 cm<sup>2</sup> V<sup>-1</sup> s<sup>-1</sup> and a subthreshold swing of ~117 mV dec<sup>-1</sup>. Based on these complementary devices, low-power inverters as well as NOR, NAND, and AND logic gates are demonstrated, confirming the feasibility of combing the n-IGZO TFTs and p-SiNW FETs for heterogeneous complementary logic integration.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2063-2066"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Unlocking the Top-Space Multi-Functionality of Thin-Film Acoustic Wave Devices 揭开薄膜声波器件的顶层空间多功能
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-14 DOI: 10.1109/LED.2026.3723922
Shuhan Chen;Fangsheng Qian;Yansong Yang
{"title":"Unlocking the Top-Space Multi-Functionality of Thin-Film Acoustic Wave Devices","authors":"Shuhan Chen;Fangsheng Qian;Yansong Yang","doi":"10.1109/LED.2026.3723922","DOIUrl":"https://doi.org/10.1109/LED.2026.3723922","url":null,"abstract":"Thin-film acoustic wave devices have substantially improved performance through bottom substrate-stack engineering, which leaves the vulnerability of interdigital transducers (IDTs) a critical challenge, especially under high-power excitation and top-space perturbations. By introducing cladding multilayers above the IDTs on a piezoelectric thin film, layered acoustic wave (LAW) devices with a symmetric acoustic-reflection structure provide strong vertical energy confinement and environmental isolation for the target modes. This architecture unlocks the top space above the IDTs for flexible functionalization. As a representative demonstration, this work presents a polymer-functionalized LAW prototype, showing that mature packaging pipelines can be simplified when inherently suppressing high-frequency, higher-order bulk wave spurious modes. With dispersion analysis and simulation, the low-acoustic-velocity and high-damping polymer is verified to be an effective medium for guiding and absorbing leaked bulk waves. The fabricated resonators provide dual functionality: spurious suppression and enhancement of the quality factor (<inline-formula> <tex-math>${Q}text {)}$ </tex-math></inline-formula> without degrading electromechanical coupling of the targeted mode. This work highlights the strong potential of versatile top-space stacking on LAW devices beyond conventional thin-film surface acoustic wave platforms.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2099-2102"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dresselhaus Spin-Orbit-Coupling-Based Spatial Electron-Spin Splitter in a Three-Layer Semiconductor Nanostructure 基于Dresselhaus自旋轨道耦合的三层半导体纳米结构空间电子自旋分离器
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-26 DOI: 10.1109/LED.2026.3725393
Ke-Yu Lu;Ya-Ping He;Li Zhang
{"title":"Dresselhaus Spin-Orbit-Coupling-Based Spatial Electron-Spin Splitter in a Three-Layer Semiconductor Nanostructure","authors":"Ke-Yu Lu;Ya-Ping He;Li Zhang","doi":"10.1109/LED.2026.3725393","DOIUrl":"https://doi.org/10.1109/LED.2026.3725393","url":null,"abstract":"We explore Goos-Hänchen effect for electron beams in a Dresselhaus spin-orbit-coupling modulated three-layer semiconductor nanostructure. Due to the spin-related effective mass, the lateral shift is found to be spin-dependent, leading to spatial separation of spins and generation of electron spin polarization. The degree of spin polarization is revealed to be modifiable via the stain or layer thickness. Based on these findings, a spatial electron spin splitter is proposed for semiconductor spintronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"1995-1998"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Porous 4H-SiC Local Avalanche Ultraviolet Photodetector With High Photo-to-Dark Current Ratio and Low Avalanche Threshold Voltage 具有高光暗比和低雪崩阈值电压的多孔4H-SiC局部雪崩紫外探测器
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-07 DOI: 10.1109/LED.2026.3721503
Guanyang Zhang;Xiaojing Huyan;Tianxiang Zhao;Haolin Lei;Yongxun Liu;Shinan Wang;Lingyan Shen;Qiang Liu;Wenjie Yu
{"title":"Porous 4H-SiC Local Avalanche Ultraviolet Photodetector With High Photo-to-Dark Current Ratio and Low Avalanche Threshold Voltage","authors":"Guanyang Zhang;Xiaojing Huyan;Tianxiang Zhao;Haolin Lei;Yongxun Liu;Shinan Wang;Lingyan Shen;Qiang Liu;Wenjie Yu","doi":"10.1109/LED.2026.3721503","DOIUrl":"https://doi.org/10.1109/LED.2026.3721503","url":null,"abstract":"In this letter, a localized-avalanche strategy for ultraviolet detection based on electrochemically etched porous 4H-SiC with grid Schottky electrodes is demonstrated. Synergistic field enhancement from porous tips and electrode-edge crowding enables avalanche multiplication at ultralow reverse bias. The fabricated porous SiC avalanche photodiode (PSC-APD) achieves an avalanche onset of approximately 12 V, a responsivity of 413.6 A/W, and an external quantum efficiency (EQE) of 176,850% at 290 nm. At 50 V, the gain reaches <inline-formula> <tex-math>$4.8times 10^{6}$ </tex-math></inline-formula> with a photo-to-dark current ratio (PDCR) of <inline-formula> <tex-math>$1.2times 10^{5}$ </tex-math></inline-formula>. TCAD simulations and comparative experiments confirm that the ultralow-voltage avalanche arises from coupled field enhancement rather than individual structural effects. This work offers a simple, effective route to low-power, high-gain UV photodetectors based on wide-bandgap semiconductors.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2071-2074"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Highly Linear and Symmetric Multilevel IGZO 2T Device Utilizing Identical Potentiation and Depression Pulses 利用相同增强和抑制脉冲的高线性和对称多电平IGZO 2T器件
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-20 DOI: 10.1109/LED.2026.3725232
Suwon Seong;Taejun Ha;Sangwook Jung;Daehwan Kang;Yoonyoung Chung
{"title":"Highly Linear and Symmetric Multilevel IGZO 2T Device Utilizing Identical Potentiation and Depression Pulses","authors":"Suwon Seong;Taejun Ha;Sangwook Jung;Daehwan Kang;Yoonyoung Chung","doi":"10.1109/LED.2026.3725232","DOIUrl":"https://doi.org/10.1109/LED.2026.3725232","url":null,"abstract":"This work presents an operation strategy for IGZO-based 2T synaptic device that enables highly linear and symmetric conductance updates using identical potentiation and depression pulses. Multilevel synaptic devices such as RRAM, PCM, and ferroelectric memory typically require level-dependent pulse modulation to compensate for their inherent nonlinearity and asymmetry, which increases peripheral circuit complexity and limits scalability. The proposed strategy overcomes this limitation by utilizing the exponential response of the read transistor to counterbalance the nonlinearity of the voltage change at the storage node. As a result, the device achieves almost linear, symmetric weight updates with identical pulses, without the need for level-specific tuning. MNIST classification simulation yielded less than 3% error and over 99% consistency with an ideal linear device, suggesting that this method can be applied to high-accuracy neural network computation.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2007-2010"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fully Phase-Change Artificial Neural Networks Based on Phase-Change Memory With Reconfigurable Activation Functions 基于可重构激活函数相变记忆的全相变人工神经网络
IF 4.6 2区 工程技术
IEEE Electron Device Letters Pub Date : 2026-10-01 Epub Date: 2026-08-14 DOI: 10.1109/LED.2026.3722897
Ruizhe Zhao;Xinbao Chen;Hanyang Chen;Hao Shu;Wenzhuo Xu;Shuliang Zhang;Xin Li;Tao Wang;Hao Tong;Xiangshui Miao
{"title":"Fully Phase-Change Artificial Neural Networks Based on Phase-Change Memory With Reconfigurable Activation Functions","authors":"Ruizhe Zhao;Xinbao Chen;Hanyang Chen;Hao Shu;Wenzhuo Xu;Shuliang Zhang;Xin Li;Tao Wang;Hao Tong;Xiangshui Miao","doi":"10.1109/LED.2026.3722897","DOIUrl":"https://doi.org/10.1109/LED.2026.3722897","url":null,"abstract":"We demonstrate an all-phase-change artificial neural network in which phase-change memory (PCM) devices simultaneously realize synaptic plasticity and reconfigurable activation-function artificial neurons. Precise control of the voltage-amplitude step size during the SET and RESET processes enables gradual conductance modulation, thereby realizing synaptic long-term potentiation (LTP) and long-term depression (LTD). More importantly, threshold switching behavior induced by larger pulse widths and larger voltage steps allows the realization of reconfigurable activation functions, including ReLU, sigmoid, and softplus. System-level simulations on the MNIST dataset demonstrate recognition accuracy exceeding 98%, comparable to those achieved using ideal software-defined activation functions, thereby validating the robustness and reliability of the all-PCM neural network. These results highlight the strong potential of PCM devices for highly integrated and multifunctional neuromorphic computing systems.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2043-2046"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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