IEEE Electron Device Letters最新文献_第5页

Enhancement-Mode GaN Monolithic Bidirectional Switch With Breakdown Voltage Over 3.3 kV

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-02-04 DOI: 10.1109/LED.2025.3539175

Yijin Guo;Yuan Qin;Ming Xiao;Matthew Porter;Qihao Song;Daniel Popa;Loizos Efthymiou;Kai Cheng;Ivan Kravchenko;Linbo Shao;Han Wang;Florin Udrea;Yuhao Zhang

{"title":"Enhancement-Mode GaN Monolithic Bidirectional Switch With Breakdown Voltage Over 3.3 kV","authors":"Yijin Guo;Yuan Qin;Ming Xiao;Matthew Porter;Qihao Song;Daniel Popa;Loizos Efthymiou;Kai Cheng;Ivan Kravchenko;Linbo Shao;Han Wang;Florin Udrea;Yuhao Zhang","doi":"10.1109/LED.2025.3539175","DOIUrl":"https://doi.org/10.1109/LED.2025.3539175","url":null,"abstract":"This work demonstrates a GaN enhancement-mode monolithic bidirectional switch (MBDS) with breakdown voltage (BV) higher than 3.3 kV in both polarities. This MBDS is realized on a dual p-GaN gate high electron mobility transistor (HEMT) platform on sapphire substrate. It features a novel dual junction termination extension design for electric field management, which is built on the p-GaN layer in the gate stack and does not require epitaxial regrowth. The GaN MBDS exhibits symmetric on-state characteristics in both directions with a threshold voltage <inline-formula> <tex-math>$({V}_{text {th}})$ </tex-math></inline-formula> of 0.6 V and a low specific on-resistance <inline-formula> <tex-math>$({R}_{text {on,sp}})$ </tex-math></inline-formula> of 5.6 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2. This device presents the highest BV, as well as one of the best BV and <inline-formula> <tex-math>${R}_{text {on,sp}}$ </tex-math></inline-formula> trade-offs, in all the reported MBDS devices. The <inline-formula> <tex-math>${R}_{text {on,sp}}$ </tex-math></inline-formula> is lower than the performance limit of conventional BDS realized by two discrete devices. This 3.3 kV GaN MBDS opens the door for developing new circuit topologies and advancing system performance in medium-voltage power electronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"556-559"},"PeriodicalIF":4.1,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Imprinted Antiferroelectric With Low Damage Process for High Performance Negative Capacitance NAND Flash Memory

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-02-04 DOI: 10.1109/LED.2025.3538562

Sangho Lee;Giuk Kim;Yunseok Nam;Yeongseok Jeong;Taeho Kim;Hunbeom Shin;Sangmok Lee;Jinho Ahn;Sanghun Jeon

{"title":"Imprinted Antiferroelectric With Low Damage Process for High Performance Negative Capacitance NAND Flash Memory","authors":"Sangho Lee;Giuk Kim;Yunseok Nam;Yeongseok Jeong;Taeho Kim;Hunbeom Shin;Sangmok Lee;Jinho Ahn;Sanghun Jeon","doi":"10.1109/LED.2025.3538562","DOIUrl":"https://doi.org/10.1109/LED.2025.3538562","url":null,"abstract":"The concept of negative capacitance (NC), originating from the intrinsic energy configuration of HZO ferroelectrics, has been predominantly utilized in logic transistors to achieve a steeper Id-Vg characteristic. Departing from these conventional approaches, we have developed an NC-NAND flash memory by integrating the NC phenomenon into the blocking oxide layer of conventional NAND flash memory. By leveraging the capacitance boosting effect of the NC-integrated blocking oxide (BO) layer, we can significantly enhance program (PGM) efficiency and lower the operating voltage of charge trap memory. In this work, we propose two combined approaches to improve the NC. First, we applied asymmetric tensile stress to the HZO layer through high-pressure annealing (HPA), thereby generating an internal electric field across the HZO layer. Additionally, we improved the polarization property of the HZO layer by employing a low-damage process during the deposition of the capping TiN electrode, minimizing interfacial damage to the HZO surface. Step-pulsed I-V measurement confirmed that the capacitance boosting effect of the NC blocking oxide with the low-damage process was improved by 16.7%, while the operating voltage was reduced by 1 V. Additionally, the NC-NAND flash memory with the low-damage process exhibited a significant higher ISPP slope characteristic.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"572-575"},"PeriodicalIF":4.1,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Inhibited String Characteristics According to Dimple Structures in 3D NAND Flash Memory

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-02-03 DOI: 10.1109/LED.2025.3531354

Jesun Park;Myounggon Kang

{"title":"Investigation of Inhibited String Characteristics According to Dimple Structures in 3D NAND Flash Memory","authors":"Jesun Park;Myounggon Kang","doi":"10.1109/LED.2025.3531354","DOIUrl":"https://doi.org/10.1109/LED.2025.3531354","url":null,"abstract":"In this letter, we investigated the boosted channel potential (V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula>) in inhibited strings with dimple (concave and convex) structures and analyzed the program (PGM) disturbance caused by <inline-formula> <tex-math>$V_{mathbf {{ch}}}$ </tex-math></inline-formula>. In concave structures, the electric field (e-field) concentrated in the spacer (SP) region, resulting in a decrease in V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula> as the degree of concavity increases. In convex structures, the e-field concentrates in the center of the word line (WL) region, boosting <inline-formula> <tex-math>$V_{mathbf {{ch}}}$ </tex-math></inline-formula> as the degree of convexity increases. This occurs due to the dispersion or concentration of the PGM voltage applied to the WL. High V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula> in the selected WL increases the potential difference (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula>) between adjacent WLs. Due to structural characteristics, the lateral e-field (E<inline-formula> <tex-math>$_{mathbf {m}}$ </tex-math></inline-formula>) is largest in concave structures, whereas the vertical e-field (E<inline-formula> <tex-math>$_{mathbf {textit {ox}}}$ </tex-math></inline-formula>) dominates in convex structures. Consequently, PGM disturb characteristics caused by hot carrier injection (HCI) are significantly degraded in convex structures.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 3","pages":"409-411"},"PeriodicalIF":4.1,"publicationDate":"2025-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Temperature Crystallization of Amorphous InGaO by Ar Plasma Treatment for Thin Film Transistors

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-01-30 DOI: 10.1109/LED.2025.3535880

Jiwon Sun;Taebin Lim;Byeonggwan Kim;Keunwoo Kim;Md. Hasnat Rabbi;Jin Jang

引用次数: 0

Bonding of Non-Planarized Fine-Pitch (10 μm) Cu Pillar Through Ag Cap

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-01-29 DOI: 10.1109/LED.2025.3535899

Zheng Zhang;Aiji Suetake;Akihiro Katsura;Ran Liu;Fupeng Huo;Rieko Okumura;Masahiko Nishijima;Chuantong Chen;Katsuaki Suganuma

{"title":"Bonding of Non-Planarized Fine-Pitch (10 μm) Cu Pillar Through Ag Cap","authors":"Zheng Zhang;Aiji Suetake;Akihiro Katsura;Ran Liu;Fupeng Huo;Rieko Okumura;Masahiko Nishijima;Chuantong Chen;Katsuaki Suganuma","doi":"10.1109/LED.2025.3535899","DOIUrl":"https://doi.org/10.1109/LED.2025.3535899","url":null,"abstract":"Fine-pitch copper (Cu) pillar interconnects have been widely adopted in flip-chip packaging to enable high-density integration. However, achieving reliable bonding with non-planarized Cu pillars is challenging which typically requires harsh bonding conditions to ensure adequate bonding quality. In this study, we successfully achieved non-planarized Cu pillar bonding under mild bonding conditions by utilizing a silver (Ag) cap as the bonding intermediate layer. Non-planarized Cu pillar chips with a pitch size of <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m were bonded using the Ag cap at <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C for 3 minutes under a low applied pressure of 5 MPa, and the shear strength can reach as high as 144.1 MPa. The bonding structures were examined using SEM and TEM, revealing a flawless bonding interface achieved by Ag interdiffusion. Furthermore, we demonstrated the applicability of the Ag cap in the packaging of a commercialized fine-pitch Cu pillar test element group (TEG) chip. The electrical resistance of the Ag-capped TEG sample was comparable to that of a solder-based structure, and remained stable after 1000 cycles of severe thermal cycling and 168 hours of highly accelerated stress test.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"644-647"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-01-29 DOI: 10.1109/LED.2025.3528280

引用次数: 0

IEEE Electron Device Letters Publication Information IEEE Electron Device Letters 出版信息

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-01-29 DOI: 10.1109/LED.2025.3526021

引用次数: 0

Wide Band Gap Semiconductors for Automotive Applications

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-01-29 DOI: 10.1109/LED.2025.3528278

引用次数: 0

5-kV SiC Deep-Implanted Superjunction MOSFETs

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-01-29 DOI: 10.1109/LED.2025.3536382

Reza Ghandi;Collin Hitchcock;Tarak Saha;Eladio Delgado;Stacey Kennerley

引用次数: 0

IEEE Transactions on Electron Devices Table of Contents

IF 4.1 2区工程技术

IEEE Electron Device Letters Pub Date : 2025-01-29 DOI: 10.1109/LED.2025.3526029

引用次数: 0