IEEE Electron Device Letters最新文献

{"title":"Monolithic Integration of Mg-Free Trench-Gate MOSFETs and μLEDs","authors":"Yan Guo;Guokai Wang;Yugang Zhou;Dunjun Chen;Hai Lu;Bin Liu;Rong Zhang;Youdou Zheng","doi":"10.1109/LED.2026.3724506","DOIUrl":"https://doi.org/10.1109/LED.2026.3724506","url":null,"abstract":"Driven by the rapid development of augmented reality (AR) and virtual reality (VR) displays, micro light-emitting diode (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LED) technology is evolving toward high brightness, high refresh rate, and high pixel density, which conventional driving and driving integration schemes can hardly meet. GaN-based monolithic drive-display integration is promising, yet existing schemes are limited by Mg doping-induced issues, poor process compatibility and high fabrication complexity. This work proposed and realized monolithically integrated Mg-free trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) and <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LEDs, which deliver a specific on-resistance of ~15.4 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm² and an on/off current ratio of <inline-formula> <tex-math>$sim {5}times {10} ^{{6}}$ </tex-math></inline-formula>, alongside turn-on/off delays of 300 ns/30 ns measured at 100 kHz. By replacing conventional Mg doping with polarization-induced doping, this approach offers high process compatibility and low fabrication complexity, paving a novel route for monolithic integration of GaN transistors and <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>LEDs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2079-2082"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deep-Ultraviolet-Coupled Floating-Gate Phototransistor for In-Sensor Visual Computing","authors":"Yezhao Zhuang;Jianlin Shi;Xiang Li;Ting Li;Yizihan Zhang;Zhipeng Zhong;Wan Wang;Yan Li;Hai Huang;Jianlu Wang;Junhao Chu","doi":"10.1109/LED.2026.3718946","DOIUrl":"https://doi.org/10.1109/LED.2026.3718946","url":null,"abstract":"Deep ultraviolet (DUV) in-sensor computing requires direct coupling between ultraviolet sensing and device-level weight updating. Floating-gate phototransistors provide an attractive platform for integrating sensing, memory, and computing. However, optical stimuli typically induce conductance potentiation, while conductance depression still relies on electrical programming, resulting in incomplete coupling between optical sensing and synaptic weight updating and introducing additional electrical programming overhead. Here, we demonstrate a MoS₂/hBN/graphene floating-gate DUV phototransistor for in-sensor computing. The device exhibits ultraviolet-selective photoresponse and stable floating-gate memory behavior. Under 254 nm illumination, controllable long-term potentiation (LTP) is achieved through photo-assisted floating-gate charge modulation. More importantly, synchronized DUV illumination and low-voltage gate pulses (8 V) enable efficient long-term depression (LTD), allowing ultraviolet inputs to participate in bidirectional weight updating. The device achieves 64 conductance states for both potentiation and depression, corresponding to 6-bit weight modulation. A convolutional neural network based on the measured device characteristics achieves over 91% accuracy in fingerprint recognition. These results demonstrate a feasible route toward DUV-coupled in-sensor visual computing.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2075-2078"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Dark-Current 4H-SiC MOS UV Photodetector With a Charge-Trapping Gate Stack by Electric Field Modulation Operation","authors":"Yao-Cheng Yang;Jenn-Gwo Hwu","doi":"10.1109/LED.2026.3721489","DOIUrl":"https://doi.org/10.1109/LED.2026.3721489","url":null,"abstract":"A 4H-SiC metal–oxide–semiconductor ultraviolet photodetector featuring an Al₂O₃/AlO<inline-formula> <tex-math>${}_{x}$ </tex-math></inline-formula>/SiO₂ charge-trapping gate stack is demonstrated for highly sensitive ultraviolet intensity monitoring. A high-quality SiO₂/SiC interface formed by intermittent spray hydrated oxidation suppresses interface defects, resulting in an ultralow dark current density (<inline-formula> <tex-math>${3}.{96} times {10}^{-{10}}~text {A}/ {cm}^{{2}}$ </tex-math></inline-formula>) under a reverse bias of -5 V. Subsequently, the upper gate dielectric layers are fabricated using thermal evaporation followed by a multi-step anodic oxidation process. Under ultraviolet illumination, photogenerated holes tunnel through the ultrathin SiO₂ layer and are stored in the oxygen-deficient AlO<inline-formula> <tex-math>${}_{x}$ </tex-math></inline-formula> layer, where the accumulated positive charges redistribute the internal oxide electric field. The continuously increasing oxide field drives a carrier transport transition from Poole–Frenkel emission to Fowler–Nordheim tunneling. The device achieves a photo-to-dark current ratio of <inline-formula> <tex-math>${8}.{0} times {10}^{{4}}$ </tex-math></inline-formula> at an ultraviolet power density of 400 W/m² and exhibits excellent linearity with a coefficient of determination (R²) exceeding 0.997. These results demonstrate a highly promising electric-field-modulation approach for robust charge-trapping-assisted ultraviolet sensing and precision intensity monitoring applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2095-2098"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Revisiting the 1-D Theoretical Limit of Wide Bandgap Semiconductor Power Devices via Variational Calculus","authors":"Bo Li;Maojun Wang;Jin Wei;Bo Shen","doi":"10.1109/LED.2026.3726530","DOIUrl":"https://doi.org/10.1109/LED.2026.3726530","url":null,"abstract":"In wide-bandgap semiconductors with strongly nonlinear impact ionization coefficients, classical monotonic doping profiles may limit the reduction of specific on-resistance (<inline-formula> <tex-math>${R}_{text {on},text {sp}}$ </tex-math></inline-formula>) under avalanche-breakdown constraints. A variational formulation shows that a non-monotonic, U-shaped profile can emerge as a candidate solution. DE optimization and TCAD simulations further support its performance advantage: a steep surface electric-field gradient spatially confines avalanche generation. Consequently, the U-shaped profile achieves a lower <inline-formula> <tex-math>${R}_{text {on},text {sp}}$ </tex-math></inline-formula> than uniform and conventional monotonic profiles while meeting the required voltage-blocking capability, providing guidance for doping-profile optimization in advanced power devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"1983-1986"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Atomistic Insights of Orbital Engineering in a-CuO Through First-Principles Study","authors":"M. Julie Therese;Vikash Mishra;Tejendra Dixit","doi":"10.1109/LED.2026.3726776","DOIUrl":"https://doi.org/10.1109/LED.2026.3726776","url":null,"abstract":"First-principles calculations were performed to investigate the structural, electronic, optical, and magnetic properties of amorphous CuO (a-CuO) through orbital engineering. The representative locally distorted CuO models were validated using the melt-quench molecular dynamics approach (MD), confirming the local structural rearrangements associated with amorphization. Partial density-of-states (PDOS) analysis reveals p-type behavior with Cu-3d states dominating the valence and conduction bands, accompanied by reduced t_2g-e_g crystal-field splitting. The reduced orbital splitting enhances Cu-3d/O-2p hybridization, leading to lower exciton binding energy extracted from the optical absorption spectra. Structural disorder also increases the magnetic moment and results in a threefold enhancement in carrier mobility. Furthermore, the Au/CuO/Au device is studied under both dark and illuminated conditions, where a-CuO demonstrates a better photocurrent density of 124.63 mA/cm² at 1 V as compared to c-CuO.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 10","pages":"2111-2114"},"PeriodicalIF":4.6,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149072277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Changes to the Editorial Board","authors":"Kelin J. Kuhn","doi":"10.1109/LED.2026.3707328","DOIUrl":"https://doi.org/10.1109/LED.2026.3707328","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1498-1498"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11627132","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"All-ALD Sequential Monolithic Integration of Selector-Free Five-Layer Ferroelectric Diodes for 3-D Cross-Point Memory","authors":"Wenjuan Zhou;Ruizhan Yan;Renhao Xue;Mansun Chan;Xiwen Liu","doi":"10.1109/LED.2026.3704279","DOIUrl":"https://doi.org/10.1109/LED.2026.3704279","url":null,"abstract":"3D cross-point (XPoint) memory is attractive for high-density integration because it retains compact two-terminal cells and bit-level accessibility during vertical scaling. However, further layer scaling of 3D XPoint architectures remains constrained by two coupled challenges: sneak-path leakage and uniform multilayer process integration. Here, we experimentally demonstrate a monolithic five-layer sequential XPoint-compatible integration route co-enabled by hafnia-based ferroelectric diodes (FeDs) and an all-ALD ultrathin stack. In this route, the intrinsic nonlinearity of FeDs suppresses half-select leakage without an external selector, while the ~10 nm-per-tier all-ALD device stack supports repeated monolithic multilayer integration through conformal growth and precise thickness control. Across all layers, the devices exhibit consistent polarization-modulated I–V hysteresis, with a high ON/OFF ratio of <inline-formula> <tex-math>$sim 10^{{3}}$ </tex-math></inline-formula>, intrinsic nonlinearity up to ~600, programming down to 50 ns, and endurance beyond <inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula> write/erase cycles. These results establish a selector-free integration route based on FeDs and all-ALD ultrathin stacks for sequential monolithic 3D XPoint memory.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1663-1666"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11570095","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strain-Induced Mobility Enhancement in Crystalline In2O3 FETs","authors":"Huangbai Liu;Yan Le;Wei Shi;Xinming Li;Gan Liu;Dong Zhang;Rui Shao;Chen Sun;Xiao Gong","doi":"10.1109/LED.2026.3699513","DOIUrl":"https://doi.org/10.1109/LED.2026.3699513","url":null,"abstract":"In this work, we demonstrate a flexible-substrate-based strategy for applying uniaxial tensile strain to indium oxide field-effect transistors (In₂O₃ FETs) and verify that strain can effectively enhance the mobility of crystalline In₂O₃ FETs. Amorphous In₂O₃ FETs fabricated by atomic layer deposition (ALD) have a mobility as high as 90 cm<inline-formula> <tex-math>${}^{{2}}cdot $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}^{-{1}}cdot $ </tex-math></inline-formula>s<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula> and remain stable under bending conditions. Post-deposition annealing (PDA) promotes the crystallization of In₂O₃, increasing the average mobility of the In₂O₃ FETs to 125 cm<inline-formula> <tex-math>${}^{{2}}cdot $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}^{-{1}}cdot $ </tex-math></inline-formula>s<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>. Upon applying uniaxial tensile strain, the average mobility of the crystalline devices significantly increases by 16%, from 125 to 145 cm<inline-formula> <tex-math>${}^{{2}}cdot $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}^{-{1}}cdot $ </tex-math></inline-formula>s<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>. Under uniaxial tensile strain, the positive bias stress (PBS) and negative bias stress (NBS) characteristics of the crystalline In₂O₃ FETs remain nearly unchanged, indicating that the applied strain does not noticeably deteriorate device reliability. It should also be noted that the crystalline In₂O₃ FETs exhibit depletion-mode characteristics, suggesting that further threshold voltage (<inline-formula> <tex-math>${V}_{text {TH}}text {)}$ </tex-math></inline-formula> optimization would be beneficial for future applications. Our investigation introduces strain-induced mobility enhancement into oxide semiconductors (OS) FETs, providing a practical approach to further improving the performance of OS FETs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1603-1606"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Gain-Stable AlN/GaN MIS-HEMTs With Pulsed N2 Plasma-Treated In-Situ SiNx Gate Dielectric","authors":"Qingyi Zhang;Ke Wei;Jianchao Wang;Sheng Zhang;Kaiyu Wang;Jiaqi Guo;Xiaoqiang He;Zhuanli Ma;Junjie Feng;Shibo Fan;Xinguo Gao;Yankui Li;Sen Huang;Xinhua Wang;Xinyu Liu","doi":"10.1109/LED.2026.3703504","DOIUrl":"https://doi.org/10.1109/LED.2026.3703504","url":null,"abstract":"In this letter, power gain-stable AlN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with pulsed N₂ plasma treated in-situ SiN_x gate dielectric were fabricated. XPS analysis and device electric field simulations indicated that a nonuniform distribution of the Si/N ratio was achieved in the vertical direction of the ultrathin dielectric after treatment, thereby reducing the peak electric field underneath the gate foot. At 3.5 GHz, the fabricated MIS-HEMT exhibits high efficiency and bias-stable linear power gain over <inline-formula> <tex-math>${V}_{text {DS}}=6$ </tex-math></inline-formula>-25 V under continuous-wave operation. Due to N₂ plasma induced modulation of the channel electric field, the linear power gain variation remains ±0.6 dB. These findings provide a viable process route for gain stabilization of GaN RF devices under changing supply voltage operations.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1539-1542"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ionic Field-Effect Transistor Achieving Large Memory Window and Enhanced Retention via Ultrathin Ozone-Oxidized Barrier Layer","authors":"Jongseon Seo;Geonhui Han;Laeyong Jung;Junghoon Park;Jongho Park;Suhwan Lim;Wanki Kim;Daewon Ha;Hyunsang Hwang","doi":"10.1109/LED.2026.3702162","DOIUrl":"https://doi.org/10.1109/LED.2026.3702162","url":null,"abstract":"We propose an ionic field-effect transistor (Ionic FET) based on a WO<inline-formula> <tex-math>${}_{text{3-}x}$ </tex-math></inline-formula>/HfOx ECRAM stack that stores information via ionic-charge-induced threshold voltage (V<inline-formula> <tex-math>${}_{text {th}}text {)}$ </tex-math></inline-formula> modulation, enabling scalable analog state control. To relax the trade-off between ion injection and retention, an ultrathin ion barrier layer formed by ozone oxidation suppresses ion back-diffusion while preserving sufficient injection. The device achieves a large memory window of ~7.6 V with linear Vth modulation, stable 3-bit multi-level operation (<inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>/<inline-formula> <tex-math>$mu lt 0.1$ </tex-math></inline-formula>), and endurance over <inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula> program/erase cycles. By raising the activation energy for ion back-diffusion, the ozone-treated barrier yields a projected room-temperature retention exceeding <inline-formula> <tex-math>$10^{{6}}$ </tex-math></inline-formula> sec.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 8","pages":"1579-1582"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}