{"title":"Enhancement-Mode GaN Monolithic Bidirectional Switch With Breakdown Voltage Over 3.3 kV","authors":"Yijin Guo;Yuan Qin;Ming Xiao;Matthew Porter;Qihao Song;Daniel Popa;Loizos Efthymiou;Kai Cheng;Ivan Kravchenko;Linbo Shao;Han Wang;Florin Udrea;Yuhao Zhang","doi":"10.1109/LED.2025.3539175","DOIUrl":"https://doi.org/10.1109/LED.2025.3539175","url":null,"abstract":"This work demonstrates a GaN enhancement-mode monolithic bidirectional switch (MBDS) with breakdown voltage (BV) higher than 3.3 kV in both polarities. This MBDS is realized on a dual p-GaN gate high electron mobility transistor (HEMT) platform on sapphire substrate. It features a novel dual junction termination extension design for electric field management, which is built on the p-GaN layer in the gate stack and does not require epitaxial regrowth. The GaN MBDS exhibits symmetric on-state characteristics in both directions with a threshold voltage <inline-formula> <tex-math>$({V}_{text {th}})$ </tex-math></inline-formula> of 0.6 V and a low specific on-resistance <inline-formula> <tex-math>$({R}_{text {on,sp}})$ </tex-math></inline-formula> of 5.6 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2. This device presents the highest BV, as well as one of the best BV and <inline-formula> <tex-math>${R}_{text {on,sp}}$ </tex-math></inline-formula> trade-offs, in all the reported MBDS devices. The <inline-formula> <tex-math>${R}_{text {on,sp}}$ </tex-math></inline-formula> is lower than the performance limit of conventional BDS realized by two discrete devices. This 3.3 kV GaN MBDS opens the door for developing new circuit topologies and advancing system performance in medium-voltage power electronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"556-559"},"PeriodicalIF":4.1,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Imprinted Antiferroelectric With Low Damage Process for High Performance Negative Capacitance NAND Flash Memory","authors":"Sangho Lee;Giuk Kim;Yunseok Nam;Yeongseok Jeong;Taeho Kim;Hunbeom Shin;Sangmok Lee;Jinho Ahn;Sanghun Jeon","doi":"10.1109/LED.2025.3538562","DOIUrl":"https://doi.org/10.1109/LED.2025.3538562","url":null,"abstract":"The concept of negative capacitance (NC), originating from the intrinsic energy configuration of HZO ferroelectrics, has been predominantly utilized in logic transistors to achieve a steeper Id-Vg characteristic. Departing from these conventional approaches, we have developed an NC-NAND flash memory by integrating the NC phenomenon into the blocking oxide layer of conventional NAND flash memory. By leveraging the capacitance boosting effect of the NC-integrated blocking oxide (BO) layer, we can significantly enhance program (PGM) efficiency and lower the operating voltage of charge trap memory. In this work, we propose two combined approaches to improve the NC. First, we applied asymmetric tensile stress to the HZO layer through high-pressure annealing (HPA), thereby generating an internal electric field across the HZO layer. Additionally, we improved the polarization property of the HZO layer by employing a low-damage process during the deposition of the capping TiN electrode, minimizing interfacial damage to the HZO surface. Step-pulsed I-V measurement confirmed that the capacitance boosting effect of the NC blocking oxide with the low-damage process was improved by 16.7%, while the operating voltage was reduced by 1 V. Additionally, the NC-NAND flash memory with the low-damage process exhibited a significant higher ISPP slope characteristic.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"572-575"},"PeriodicalIF":4.1,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Investigation of Inhibited String Characteristics According to Dimple Structures in 3D NAND Flash Memory","authors":"Jesun Park;Myounggon Kang","doi":"10.1109/LED.2025.3531354","DOIUrl":"https://doi.org/10.1109/LED.2025.3531354","url":null,"abstract":"In this letter, we investigated the boosted channel potential (V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula>) in inhibited strings with dimple (concave and convex) structures and analyzed the program (PGM) disturbance caused by <inline-formula> <tex-math>$V_{mathbf {{ch}}}$ </tex-math></inline-formula>. In concave structures, the electric field (e-field) concentrated in the spacer (SP) region, resulting in a decrease in V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula> as the degree of concavity increases. In convex structures, the e-field concentrates in the center of the word line (WL) region, boosting <inline-formula> <tex-math>$V_{mathbf {{ch}}}$ </tex-math></inline-formula> as the degree of convexity increases. This occurs due to the dispersion or concentration of the PGM voltage applied to the WL. High V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula> in the selected WL increases the potential difference (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<inline-formula> <tex-math>$_{mathbf {textit {ch}}}$ </tex-math></inline-formula>) between adjacent WLs. Due to structural characteristics, the lateral e-field (E<inline-formula> <tex-math>$_{mathbf {m}}$ </tex-math></inline-formula>) is largest in concave structures, whereas the vertical e-field (E<inline-formula> <tex-math>$_{mathbf {textit {ox}}}$ </tex-math></inline-formula>) dominates in convex structures. Consequently, PGM disturb characteristics caused by hot carrier injection (HCI) are significantly degraded in convex structures.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 3","pages":"409-411"},"PeriodicalIF":4.1,"publicationDate":"2025-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiwon Sun;Taebin Lim;Byeonggwan Kim;Keunwoo Kim;Md. Hasnat Rabbi;Jin Jang
{"title":"Low-Temperature Crystallization of Amorphous InGaO by Ar Plasma Treatment for Thin Film Transistors","authors":"Jiwon Sun;Taebin Lim;Byeonggwan Kim;Keunwoo Kim;Md. Hasnat Rabbi;Jin Jang","doi":"10.1109/LED.2025.3535880","DOIUrl":"https://doi.org/10.1109/LED.2025.3535880","url":null,"abstract":"We investigated the effect of Ar plasma treatment on the crystallization of indium-gallium-oxide (IGO) thin films. Ar plasma treatment accelerates the crystallization of amorphous IGO at <inline-formula> <tex-math>$350~^{circ }$ </tex-math></inline-formula>C, as confirmed by XRD analysis. The crystalline IGO TFT using Ar plasma treatment exhibited field-effect mobility (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula><inline-formula> <tex-math>$_{text {FE}}text {)}$ </tex-math></inline-formula> of 43.2 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s and subthreshold swing (SS) of 0.11 V/dec. In addition, IGO TFTs showed excellent operation stabilities under both positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) conditions. These results demonstrate that Ar plasma treatment is a promising technique for achieving high-performance IGO TFTs at low temperature, making it suitable for flexible display application.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"596-599"},"PeriodicalIF":4.1,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bonding of Non-Planarized Fine-Pitch (10 μm) Cu Pillar Through Ag Cap","authors":"Zheng Zhang;Aiji Suetake;Akihiro Katsura;Ran Liu;Fupeng Huo;Rieko Okumura;Masahiko Nishijima;Chuantong Chen;Katsuaki Suganuma","doi":"10.1109/LED.2025.3535899","DOIUrl":"https://doi.org/10.1109/LED.2025.3535899","url":null,"abstract":"Fine-pitch copper (Cu) pillar interconnects have been widely adopted in flip-chip packaging to enable high-density integration. However, achieving reliable bonding with non-planarized Cu pillars is challenging which typically requires harsh bonding conditions to ensure adequate bonding quality. In this study, we successfully achieved non-planarized Cu pillar bonding under mild bonding conditions by utilizing a silver (Ag) cap as the bonding intermediate layer. Non-planarized Cu pillar chips with a pitch size of <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m were bonded using the Ag cap at <inline-formula> <tex-math>$200~^{circ }$ </tex-math></inline-formula>C for 3 minutes under a low applied pressure of 5 MPa, and the shear strength can reach as high as 144.1 MPa. The bonding structures were examined using SEM and TEM, revealing a flawless bonding interface achieved by Ag interdiffusion. Furthermore, we demonstrated the applicability of the Ag cap in the packaging of a commercialized fine-pitch Cu pillar test element group (TEG) chip. The electrical resistance of the Ag-capped TEG sample was comparable to that of a solder-based structure, and remained stable after 1000 cycles of severe thermal cycling and 168 hours of highly accelerated stress test.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"644-647"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29","authors":"","doi":"10.1109/LED.2025.3528280","DOIUrl":"https://doi.org/10.1109/LED.2025.3528280","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 2","pages":"324-324"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857428","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/LED.2025.3528278","DOIUrl":"https://doi.org/10.1109/LED.2025.3528278","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 2","pages":"320-321"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857427","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"5-kV SiC Deep-Implanted Superjunction MOSFETs","authors":"Reza Ghandi;Collin Hitchcock;Tarak Saha;Eladio Delgado;Stacey Kennerley","doi":"10.1109/LED.2025.3536382","DOIUrl":"https://doi.org/10.1109/LED.2025.3536382","url":null,"abstract":"This work presents the development and characterization of 5kV deep-implanted SiC superjunction (SJ) MOSFETs. In these switches, the <inline-formula> <tex-math>$36mu $ </tex-math></inline-formula>m deep n-type and p-type SJ pillars were formed using three rounds of epitaxial overgrowth and ultra-high-energy implantation (UHEI). We successfully fabricated SJ MOSFETs with pillar pitches of <inline-formula> <tex-math>$8mu $ </tex-math></inline-formula>m, <inline-formula> <tex-math>$10mu $ </tex-math></inline-formula>m, and <inline-formula> <tex-math>$12mu $ </tex-math></inline-formula>m, achieving an R<inline-formula> <tex-math>$_{mathsf {textbf {on,sp}}}$ </tex-math></inline-formula> of 9.5 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> <inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2 at room temperature, which is 25% below the SiC unipolar limit. The devices also demonstrated sharp avalanche breakdown at 5.1kV with low leakage current density.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 4","pages":"553-555"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IEEE Transactions on Electron Devices Table of Contents","authors":"","doi":"10.1109/LED.2025.3526029","DOIUrl":"https://doi.org/10.1109/LED.2025.3526029","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 2","pages":"325-C3"},"PeriodicalIF":4.1,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857344","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}