{"title":"A High-Density 3-D Capacitor Using Through Glass Via Structure","authors":"Su-Geun Kim;Sung-Chai Yoo;Jeongwon Oh;Byung-Wook Min;Jong-Min Yook","doi":"10.1109/LED.2025.3599178","DOIUrl":null,"url":null,"abstract":"Glass substrates offer excellent properties for high-density package applications due to their low coefficient of thermal expansion, nanometer-scale surface flatness, and minimal dielectric loss. These characteristics make glass substrates well-suited for integrated passive devices. This study presents a high-density 3D via capacitor embedded in a glass substrate. The through-hole glass vias (TGVs) are conformally lined with a TiN/HfO2/TiN stack, using processes that are fully compatible with standard TGV fabrication techniques. The fabricated device exhibited an aspect ratio of 16:1 and achieved a measured capacitance of up to 9.7 nF within a <inline-formula> <tex-math>$275~\\mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$\\times 220~\\mu $ </tex-math></inline-formula>m area, corresponding to a capacitance density of 160.33 nF/mm2. Measured electrical performance included an ESR of 237 m <inline-formula> <tex-math>$\\Omega $ </tex-math></inline-formula> and a breakdown voltage of 6.31 ± 0.5 V, demonstrating its suitability for decoupling and power integrity applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1920-1923"},"PeriodicalIF":4.5000,"publicationDate":"2025-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11126088/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Glass substrates offer excellent properties for high-density package applications due to their low coefficient of thermal expansion, nanometer-scale surface flatness, and minimal dielectric loss. These characteristics make glass substrates well-suited for integrated passive devices. This study presents a high-density 3D via capacitor embedded in a glass substrate. The through-hole glass vias (TGVs) are conformally lined with a TiN/HfO2/TiN stack, using processes that are fully compatible with standard TGV fabrication techniques. The fabricated device exhibited an aspect ratio of 16:1 and achieved a measured capacitance of up to 9.7 nF within a $275~\mu $ m $\times 220~\mu $ m area, corresponding to a capacitance density of 160.33 nF/mm2. Measured electrical performance included an ESR of 237 m $\Omega $ and a breakdown voltage of 6.31 ± 0.5 V, demonstrating its suitability for decoupling and power integrity applications.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.