A Single-Layer Nested-Coil On-Chip Transformer for Cost-Effective High-Voltage Digital Isolation

Abstract

In this letter, a single-layer nested-coil on-chip transformer (NCOCT) is proposed and demonstrated for cost-effective high-voltage digital isolation. The two nested planar spiral coils are implemented in a single metal layer for cost-effective fabrication. The metal layer is sandwiched between two isolation layers which block the breakdown paths. The intrinsic distance through isolation (DTI) is determined by the lateral layout distance between the two coils, which makes it easy to achieve high-voltage isolation. The fabricated 0.64-mm2 NCOCT achieved coil inductances of 28/27 nH, as well as a high isolation capability of 12 kV DC and 8 kVrms AC with a DTI of $37.2~\mu $ m. The small coupling factor of 0.3 and the small primary-to-secondary parasitic capacitance of 0.35 pF provides a similar signal-to-common-mode-transient-noise ratio compared with conventional transformer structures.