ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures最新文献

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An investigation into the nonquasistatic effects in MOS devices with on-wafer S-parameter techniques 基于片上s参数技术的MOS器件非准静态效应研究
R. Singh, A. Juge, R. Joly, G. Mortin
{"title":"An investigation into the nonquasistatic effects in MOS devices with on-wafer S-parameter techniques","authors":"R. Singh, A. Juge, R. Joly, G. Mortin","doi":"10.1109/ICMTS.1993.292899","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292899","url":null,"abstract":"The high-frequency characteristics of MOS devices are investigated with a view to the identification of nonquasistatic (NQS) effects considering the Bagheri and Tsividis I-order NQS model as a reference. An exhaustive set of data is analyzed. It indicates the existence of NQS effects in long- as well as short-channel devices. Significant differences are observed between a charge based quasi-static model and measurements for a long-channel (25- mu m) device. A deembedding technique is suggested to observe the intrinsic device behavior up to a higher range of frequencies.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124286181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A moveable shielding box adaptable to commercial automatic wafer probers 一种可移动屏蔽盒,适用于商用自动晶圆探测器
M. Lozano, C. Cané, J. Santander, I. Gràcia, E. Lora-Tamayo
{"title":"A moveable shielding box adaptable to commercial automatic wafer probers","authors":"M. Lozano, C. Cané, J. Santander, I. Gràcia, E. Lora-Tamayo","doi":"10.1109/ICMTS.1993.292917","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292917","url":null,"abstract":"A compact movable shielding box designed to be easily adapted to commercial automatic wafer probers is presented. This design allows the realization of automatic wafer mapping in a shielded area. It only covers the chuck and the prober area, avoiding the use of cumbersome Faraday boxes. Its design is explained, and the effective shielding capabilities are demonstrated by measuring subthreshold currents.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132597877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of real defect outlines for defect size distribution and yield prediction 真实缺陷轮廓的建模,用于缺陷尺寸分布和良率预测
C. Hess, A. Strole
{"title":"Modeling of real defect outlines for defect size distribution and yield prediction","authors":"C. Hess, A. Strole","doi":"10.1109/ICMTS.1993.292890","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292890","url":null,"abstract":"For efficient yield, prediction defects are usually modeled by circular disks or squares. A more accurate model is presented. It considers the real outline of physical defects. To utilize this model, only the maximum and the minimum extension of detected defects must be determined. That can be done easily using a checkerboard test structure including a defect localization procedure. The accuracy of the predicted number of defects can be substantially enhanced by modeling real defect outlines with this elliptical model. If the elliptical model of the defect outlines is applied, the defect size distribution implicitly contains information about the physical defect outlines. Hence, for yield prediction the inspection of defect outlines can be omitted.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134044101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The use of low-level pre-tunneling currents to characterize thin oxide wearout and breakdown 使用低水平的预隧穿电流来表征薄氧化物的磨损和击穿
D. Dumin, J. Maddux, R. Subramoniam, R. S. Scott, D. Wong
{"title":"The use of low-level pre-tunneling currents to characterize thin oxide wearout and breakdown","authors":"D. Dumin, J. Maddux, R. Subramoniam, R. S. Scott, D. Wong","doi":"10.1109/ICMTS.1993.292922","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292922","url":null,"abstract":"It is found that low-level, pre-tunneling currents flowing through thin silicon oxide films can be used to characterize wearout caused by high voltage stressing. The low-level transient currents that flow after voltage pulses are removed from the oxides are used to measure the density and distribution of traps that have been generated in the films by high voltage stressing. The increase in the low-level, pre-tunneling current that flows through the oxide after the stress is directly proportional to the number of traps that have been generated. This increase in the low-level current leads to the development of a model that relates the physical wearout caused during high voltage or high current stressing to the measured statistical time dependent dielectric breakdown (TDDB) distributions. Wearout is described in terms of the traps that are generated within the oxide during wearout.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132829715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A flexible test structure evaluation system for reliability data analysis 一种用于可靠性数据分析的柔性试验结构评估系统
M. Mori, Y. Kuriyama, N. Shiono
{"title":"A flexible test structure evaluation system for reliability data analysis","authors":"M. Mori, Y. Kuriyama, N. Shiono","doi":"10.1109/ICMTS.1993.292921","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292921","url":null,"abstract":"A test structure evaluation system with powerful data processing capability is developed for effective measurement data acquisition and reliability data analysis. Data analysis can be performed quickly with a unified data format customized to reliability data. A unified, flexible system is achieved by networking discrete measuring systems and by generalizing common routines in measurement programs.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126256758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A direct, reliable, measurement-based technique for the extraction of an on-chip HBT dummy structure equivalent circuit 一种直接,可靠,基于测量的技术,用于提取片上HBT假结构等效电路
K. Lu, P. Perry, T. Brazil
{"title":"A direct, reliable, measurement-based technique for the extraction of an on-chip HBT dummy structure equivalent circuit","authors":"K. Lu, P. Perry, T. Brazil","doi":"10.1109/ICMTS.1993.292898","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292898","url":null,"abstract":"A reliable measurement-based technique is introduced to extract dummy structure modeling parameters which are used to deembed the intrinsic S-parameters of an on-chip heterojunction bipolar transistor (HBT) device. The entire parameter set of the dummy structure equivalent circuit is obtained by direct processing of the measurement data. This avoids the need for computer optimization which often produces unrealistic results. An example is given to demonstrate the method, and the structure model is applied to reveal the intrinsic device S-parameters of an HBT.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117044645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The use of test masks in the analysis of device yields 在器件产量分析中使用测试掩模
S. J. Rhodes, G.C. Day
{"title":"The use of test masks in the analysis of device yields","authors":"S. J. Rhodes, G.C. Day","doi":"10.1109/ICMTS.1993.292920","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292920","url":null,"abstract":"A product specific test mask is used to analyze circuit yield and associate it with device parameter yield, which can then more easily be related to process failure. Once a consistent failure mode has been identified, it is found that a problem specific test mask is also required to finally effect a solution. An example of this yield diagnosis methodology is described based on a nonvolatile static RAM (SRAM) circuit.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132649940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs) 高恒压应力引起的时间依赖退化的结评价(dram)
J. Mitsuhashi, J. Komori, T. Eimori, H. Koyama
{"title":"Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs)","authors":"J. Mitsuhashi, J. Komori, T. Eimori, H. Koyama","doi":"10.1109/ICMTS.1993.292883","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292883","url":null,"abstract":"Wafer-level time dependent junction degradation (TDJD) is investigated as a technique for evaluating junction reliability. The TDJD phenomenon due to latent defects is revealed by high constant voltage stressing, in the same way that the TDDB test determines the long-term reliability of the junction. Latent defects enhance the junction degradation due to TDJD. Electrons trapped at the perimeter of a junction degrade junction characteristics. Although the perimeter of a junction is composed with local oxidation of silicon (LOCOS) and/or gate edge, the gate edge is found to be more significant for the TDJD characteristics.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A test pattern for three-dimensional latch-up analysis 三维闭锁分析的测试模式
I. De Munari, R. Menozzi, M. Davoli, F. Fantini
{"title":"A test pattern for three-dimensional latch-up analysis","authors":"I. De Munari, R. Menozzi, M. Davoli, F. Fantini","doi":"10.1109/ICMTS.1993.292886","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292886","url":null,"abstract":"By means of both cross-section and layout two-dimensional (2D) numerical simulations, three-dimensional (3D) latch-up interactions are demonstrated to significantly influence the latch-up behavior of a typical CMOS structure. A 3D latch-up test pattern is designed to allow the experimental study of such effects. The first measurement results show complex behaviors that can be overlooked if common 2D test patterns are used.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"114 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116639428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test structure for the in-plane locations of project features with nanometer-level accuracy traceable to a coordinate measurement system 工程特征面内位置的测试结构,具有纳米级精度,可追溯至坐标测量系统
M. Cresswell, R. Allen, L. W. Linholm, C. Ellenwood, W. B. Penzes, E. Teague
{"title":"Test structure for the in-plane locations of project features with nanometer-level accuracy traceable to a coordinate measurement system","authors":"M. Cresswell, R. Allen, L. W. Linholm, C. Ellenwood, W. B. Penzes, E. Teague","doi":"10.1109/ICMTS.1993.292910","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292910","url":null,"abstract":"A new test structure is reported. It is designed to measure the positions of the images of an array of features projected from a mask into a resist film on substrate with accuracy better than 10 nm. The resist film on the substrate covers a nominally matching array of partially formed versions of the test structure prepatterned in a conducting film. Instances of the finished structure are formed on the substrate by further selective removal of conducting material from the partially formed test structures where they are overlaid by images of the fiducial marks on the mask. At each array point, the feature of the completed test structure that is defined by the overlay of the image of the fiducial marks on the mask is called the pointer. The part of the partially formed test structure that is unaffected by the overlay of the images of the fiducial marks on the mask serves as a ruler. Electrical testing accurately provides the precise location of the pointer relative to the ruler within each test structure. The locations of the rulers prepatterned on the substrate are determined with a coordinate measurement system (CMS) called the NIST (National Institute of Standards and Technology) Molecular Measuring Machine (M-Cubed).<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131889184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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