高恒压应力引起的时间依赖退化的结评价(dram)

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI:10.1109/ICMTS.1993.292883

J. Mitsuhashi, J. Komori, T. Eimori, H. Koyama

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引用次数: 1

摘要

研究了晶圆级时间依赖结退化(TDJD)作为评估结可靠性的技术。由于潜在缺陷导致的tdd现象是通过高恒压应力揭示出来的，与TDDB测试决定结的长期可靠性相同。潜在缺陷加剧了TDJD引起的结退化。被困在结周长的电子会降低结的特性。虽然结的周长由硅的局部氧化(LOCOS)和/或栅边组成，但栅边对TDJD特性更为重要。

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Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs)

Wafer-level time dependent junction degradation (TDJD) is investigated as a technique for evaluating junction reliability. The TDJD phenomenon due to latent defects is revealed by high constant voltage stressing, in the same way that the TDDB test determines the long-term reliability of the junction. Latent defects enhance the junction degradation due to TDJD. Electrons trapped at the perimeter of a junction degrade junction characteristics. Although the perimeter of a junction is composed with local oxidation of silicon (LOCOS) and/or gate edge, the gate edge is found to be more significant for the TDJD characteristics.<>

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ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

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