A test pattern for three-dimensional latch-up analysis

Abstract

By means of both cross-section and layout two-dimensional (2D) numerical simulations, three-dimensional (3D) latch-up interactions are demonstrated to significantly influence the latch-up behavior of a typical CMOS structure. A 3D latch-up test pattern is designed to allow the experimental study of such effects. The first measurement results show complex behaviors that can be overlooked if common 2D test patterns are used.<>