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ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures最新文献

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A test structure for transferring timing setup between digital IC testers 一种用于在数字集成电路测试仪之间传递时序设置的测试结构
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292916
L. Allodi, G. Chiorboli, G. Franco, C. Morandi, F. Venturi
{"title":"A test structure for transferring timing setup between digital IC testers","authors":"L. Allodi, G. Chiorboli, G. Franco, C. Morandi, F. Venturi","doi":"10.1109/ICMTS.1993.292916","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292916","url":null,"abstract":"A test structure is designed in order to investigate an original procedure for accurately reproducing on a target automatic test equipment (ATE) for digital ICs the same timing setup used by a source ATE. The aim is to settle manufacturer/customer contestations. Implementation in a 2.4- mu m CMOS technology is reported, together with preliminary experimental results.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"48 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132829594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design considerations for a test structure which can be used to determine the optimum focus 可用于确定最佳焦点的测试结构的设计考虑
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292907
A. Walton, M. Fallon, J. Stevenson, A. Ross
{"title":"Design considerations for a test structure which can be used to determine the optimum focus","authors":"A. Walton, M. Fallon, J. Stevenson, A. Ross","doi":"10.1109/ICMTS.1993.292907","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292907","url":null,"abstract":"A test structure which can be used to optimize the focus of wafer steppers is described. Simulation is used to determine the optimum setting for some of the design parameters in order to ensure maximum sensitivity of the device. Preliminary results indicate that the resistance of the structure is sensitive to changes in both exposure and focus, but that the 'noise' on the measurement masks the true sensitivity.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131324500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A methodology for pre-determination of bipolar SPICE model parameters in BiCMOS technology BiCMOS技术中双极SPICE模型参数的预确定方法
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292900
S. Aggarwal, A. Juge
{"title":"A methodology for pre-determination of bipolar SPICE model parameters in BiCMOS technology","authors":"S. Aggarwal, A. Juge","doi":"10.1109/ICMTS.1993.292900","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292900","url":null,"abstract":"In order to minimize measurement efforts, a methodology is proposed for obtaining SPICE (simulation program with IC emphasis) model parameters for bipolar devices of varying sizes available in a BiCMOS technology. The methodology is based on the partitioning of terminal currents and capacitances into area- and perimeter-dependent unit parameters. Model parameters are provided for all devices in a manner consistent with controllable accuracy indicators. This approach allows pre-determination of the model parameters for the devices which are yet to be fabricated.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116978192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced gate-controlled-diode current (EGCDC) measurement 增强的门控二极管电流(EGCDC)测量
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292895
C. Viswanathan, Jen-tai Hsu, P. Aum, D. Chan
{"title":"Enhanced gate-controlled-diode current (EGCDC) measurement","authors":"C. Viswanathan, Jen-tai Hsu, P. Aum, D. Chan","doi":"10.1109/ICMTS.1993.292895","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292895","url":null,"abstract":"A technique for the measurement of the gate-controlled-diode-current (GCDC) in short-channel MOS transistors is described. This technique uses the internal bipolar action of the MOS transistor to amplify the GCDC, thereby extending the sensitivity of the measurement. Results of measurements on small geometry devices, as well as on larger devices, are given. A model based on parasitic bipolar transistor action is given for the enhanced gate-controlled diode current (EGCDC).<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133935494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An implementation of CMOS design for testability techniques for non stuck-at faults 非卡滞故障可测试性技术的CMOS设计实现
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292887
M. Lanzoni, M. Favalli, P. Olivo, B. Riccò
{"title":"An implementation of CMOS design for testability techniques for non stuck-at faults","authors":"M. Lanzoni, M. Favalli, P. Olivo, B. Riccò","doi":"10.1109/ICMTS.1993.292887","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292887","url":null,"abstract":"An experimental analysis of design for testability (DFT) techniques used to detect the presence of faulty resistive paths throughout CMOS ICs is presented. Current monitoring, delay fault testing and new design for testability (DFT) techniques are compared by means of a chip designed ad hoc. It allows simulation via hardware of the presence of resistive bridgings within standard functional blocks. The results suggest that specific DFT techniques offer considerable advantages over more conventional approaches.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127847517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test structure metrology of homogeneous contamination 均质污染试验结构计量
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292919
H. Parks, peixiong zhao, R. Craigin, R. Jones, P. Resnick
{"title":"Test structure metrology of homogeneous contamination","authors":"H. Parks, peixiong zhao, R. Craigin, R. Jones, P. Resnick","doi":"10.1109/ICMTS.1993.292919","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292919","url":null,"abstract":"Test structures are fabricated with known amounts of iron and copper contamination in the pregate oxide clean of a 1.25- mu m CMOS process. Diode and capacitor measurements indicate device degradation in the case of copper, confirming deposition studies indicating that copper deposits from HF solutions. Iron contaminated wafers show no contamination-related device effects, in support of theoretical predictions and of deposition studies indicating that iron does not deposit from HF solutions. The importance and potential usefulness of test structures as homogeneous contamination monitors is illustrated though device modeling of the contamination effects.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127986854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Prediction of dark currents in actual devices using new test structure 使用新测试结构预测实际器件中的暗电流
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292925
K. Shibusawa, N. Murakami, T. Mori, T. Ajioka
{"title":"Prediction of dark currents in actual devices using new test structure","authors":"K. Shibusawa, N. Murakami, T. Mori, T. Ajioka","doi":"10.1109/ICMTS.1993.292925","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292925","url":null,"abstract":"A test structure with four gate-controlled diodes (GCDs) and two junction diodes (with different dimensions) is designed in order to divide a dark current in actual devices into five components corresponding to device structure. Gate bias and temperature dependence reveal that the diffusion current from bulk is dominant in area regions. The G-R current is observed in the local oxidation of silicon (LOCOS) edge and gate edge. When applied to a CCD device, this method can predict the dark current in actual devices. It is found that the noise electron accumulated in one refresh cycle in dynamic RAMs (DRAMs) is increased according to DRAM generation, and that the main component originates from the source/field border region.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131937594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Process windows for convenient in-process monitoring of oxide and polysilicon etches 过程窗口，方便在过程中监测氧化物和多晶硅蚀刻
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292914
K. Golshan, H. Tigelaar, M. Harward
{"title":"Process windows for convenient in-process monitoring of oxide and polysilicon etches","authors":"K. Golshan, H. Tigelaar, M. Harward","doi":"10.1109/ICMTS.1993.292914","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292914","url":null,"abstract":"Process monitor window test structures are developed to standardize and to facilitate the in-process monitoring of oxide and polysilicon etches. With training, the operator can easily monitor and tune the etching process visually using these process windows. If a standard set of process monitor structures is developed for each technology and placed on all reticle sets using that technology, operators are provided with an easily recognized place to make their measurements. These windows standardize the measurement taking process, thereby reducing errors and improving quality.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125677748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An easy technique for determining diffusion and generation-recombination components of the current of pn junctions for better modelling 一个简单的技术来确定扩散和产生-重组组件的pn结电流更好的建模
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292926
C. Cané, M. Lozano, I. Gràcia, J. Santander, E. Lora-Tamayo
{"title":"An easy technique for determining diffusion and generation-recombination components of the current of pn junctions for better modelling","authors":"C. Cané, M. Lozano, I. Gràcia, J. Santander, E. Lora-Tamayo","doi":"10.1109/ICMTS.1993.292926","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292926","url":null,"abstract":"A method for determining the diffusion and generation-recombination components of the current of a pn junction is presented. It is based on the double derivation of the I-V characteristic and obtains two parameters which can be used for a better modeling of this device, compared with the standard model that includes the extrapolated saturation current and the ideality factor. The technique detects the point where high injection and series resistance acquire importance, in order to extract the desired parameters below this point. As the technique is fully automatic, it is suitable when wafer mapping and statistical data are desired. The system can be applied to any silicon pn junction and the results of a well junction of a standard CMOS circuit are presented as an example.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117048505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Evaluation of metallization systems with test structures and yield modeling 用试验结构和良率模型评价金属化系统
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292891
C. A. DeLoach, H. Parks, S. Beck
{"title":"Evaluation of metallization systems with test structures and yield modeling","authors":"C. A. DeLoach, H. Parks, S. Beck","doi":"10.1109/ICMTS.1993.292891","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292891","url":null,"abstract":"Comb test structures are used to evaluate three metal systems for IC use. Defects are analyzed based on density alone using a simple noncluster Poisson yield model and for clustering as well as using a negative binomial yield model. Results show that to accurately evaluate the highest yielding metal system at VLSI chip sizes, defects must be separated by type and evaluated in terms of clustering as well as defect density.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116740567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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