An implementation of CMOS design for testability techniques for non stuck-at faults

Abstract

An experimental analysis of design for testability (DFT) techniques used to detect the presence of faulty resistive paths throughout CMOS ICs is presented. Current monitoring, delay fault testing and new design for testability (DFT) techniques are compared by means of a chip designed ad hoc. It allows simulation via hardware of the presence of resistive bridgings within standard functional blocks. The results suggest that specific DFT techniques offer considerable advantages over more conventional approaches.<>