一种用于在数字集成电路测试仪之间传递时序设置的测试结构

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI:10.1109/ICMTS.1993.292916

L. Allodi, G. Chiorboli, G. Franco, C. Morandi, F. Venturi

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引用次数: 0

摘要

设计了一种测试结构，以研究在数字集成电路的目标自动测试设备(ATE)上精确再现与源ATE使用的相同时序设置的原始程序。其目的是解决制造商/客户的争议。报道了在2.4 μ m CMOS技术上的实现，并给出了初步的实验结果

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A test structure for transferring timing setup between digital IC testers

A test structure is designed in order to investigate an original procedure for accurately reproducing on a target automatic test equipment (ATE) for digital ICs the same timing setup used by a source ATE. The aim is to settle manufacturer/customer contestations. Implementation in a 2.4- mu m CMOS technology is reported, together with preliminary experimental results.<>

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ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

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