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ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures最新文献

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A low frequency AC method to measure the doping profile in the channel region of a MOSFET with general extendability to the semiconductor surface 一种用于测量MOSFET沟道区域掺杂分布的低频交流方法，具有一般可扩展到半导体表面
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292880
J. Kendall, J. Kolk, A. Boothroyd, D. A. Vincent
{"title":"A low frequency AC method to measure the doping profile in the channel region of a MOSFET with general extendability to the semiconductor surface","authors":"J. Kendall, J. Kolk, A. Boothroyd, D. A. Vincent","doi":"10.1109/ICMTS.1993.292880","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292880","url":null,"abstract":"A method is presented to measure the doping profile in the channel region of a MOSFET from the small signal AC parameter, dV/sub SB//dV/sub GS/, and to display the doping profile on the screen of a parameter analyzer. The depletion depth is directly proportional to dV/sub SB//dV/sub GS/, and the doping density is proportional to its first V/sub GS/ derivative. It is shown how the method can be extended to determine the doping profile near the semiconductor surface. This extension method is applicable to any MOSFET dopant profiling technique based on measurements near threshold.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133208602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-voltage termination-structure design using a test chip and two-dimensional simulation 采用测试芯片设计高压终端结构并进行二维仿真
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292896
peixiong zhao, S. Kosier, B. Salik, K. Galloway, C. F. Wheatley, D. J. Burton
{"title":"High-voltage termination-structure design using a test chip and two-dimensional simulation","authors":"peixiong zhao, S. Kosier, B. Salik, K. Galloway, C. F. Wheatley, D. J. Burton","doi":"10.1109/ICMTS.1993.292896","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292896","url":null,"abstract":"The variation in breakdown voltage for high-voltage diodes with varying field-ring termination designs is examined using a junction-termination test chip. The experimental results are explained using two-dimensional simulation of the diode reverse I-V characteristics. A test chip is used to examine the performances of ten different floating-ring termination structures. Both three-ring and six-ring structures are included. For all substrate resistivities, the best termination structure is able to provide the nominal breakdown voltage, while less effective designs are insufficient. In general, the best performance is obtained from structures with closely spaced rings. The experimental results also point toward possible improvements in the termination structures (closer ring spacing).<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123997933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI device parameters extraction for radiation hardness modeling with SPICE 基于SPICE的超大规模集成电路器件辐射硬度建模参数提取
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292901
K. O. Petrosjanc, I. Kharitonov
{"title":"VLSI device parameters extraction for radiation hardness modeling with SPICE","authors":"K. O. Petrosjanc, I. Kharitonov","doi":"10.1109/ICMTS.1993.292901","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292901","url":null,"abstract":"For purposes of radiation hardness modeling with SPICE (simulation program with IC emphasis), the procedures for bipolar and MOS transistor model parameter definition are described. The procedures are derived for standard and modified SPICE models. Examples of parameter extraction for irradiated devices are given.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"314 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128563050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Characterization of SOI MOSFETs by gate capacitance measurements 栅极电容测量法表征SOI mosfet
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292906
D. Flandre, B. Gentinne
{"title":"Characterization of SOI MOSFETs by gate capacitance measurements","authors":"D. Flandre, B. Gentinne","doi":"10.1109/ICMTS.1993.292906","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292906","url":null,"abstract":"A technique to extract the film thickness of silicon on insulator (SOI) MOSFETs from gate capacitance measurements on very large devices is validated through a detailed study including 2D numerical AC device simulations. A new extraction formula is developed. It enhances the precision of the method and extends its applicability to smaller channel lengths, and hence conventional test transistors. An original method unique to SOI MOSFETs is proposed to extract simultaneously the effective gate length and gate oxide and film thicknesses from a set of C-V measurements on transistors of varying lengths. The capabilities of the gate capacitance technique for extracting the physical strong inversion threshold voltage and the film doping level of SOI MOSFETs are demonstrated.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125057828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A direct extraction algorithm for a submicron MOS transistor model 亚微米MOS晶体管模型的直接提取算法
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292928
P. R. Karlsson, K. Jeppson
{"title":"A direct extraction algorithm for a submicron MOS transistor model","authors":"P. R. Karlsson, K. Jeppson","doi":"10.1109/ICMTS.1993.292928","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292928","url":null,"abstract":"A four-point technique for direct extraction of the linear region model parameters of submicron transistors is presented. The choice of data points for minimizing sensitivity to measurement noise is discussed. For a submicron transistor model where a second order mobility reduction factor is included to model the quadratic gate voltage dependence, direct extraction of the four linear-region parameters is possible using only four data points. This means that efficient parameter extraction is facilitated and that this type of submicron transistor model can be used in production control.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124093995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Power lateral DMOS transistor test structures 功率横向DMOS晶体管测试结构
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292897
S. Hidalgo, J. Fernandez, P. Godignon, J. Rebollo, J. Millán
{"title":"Power lateral DMOS transistor test structures","authors":"S. Hidalgo, J. Fernandez, P. Godignon, J. Rebollo, J. Millán","doi":"10.1109/ICMTS.1993.292897","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292897","url":null,"abstract":"The design and the fabrication of LDMOS test structures are discussed. The impact of cell dimensions and epilayer properties on the device characteristics is shown, together with the optimization of V/sub BR//R/sub ON/ trade-off. The influence of device layout, edge device termination and geometrical dimensions are investigated with these test structures. Square, circular, single-finger, multi-finger, and waved gate layouts are considered in the test monitor chip. The fabrication process is a conventional poly-gate double diffusion MOS (DMOS) process based on a double diffusion for the active channel formation. The resurfed LDMOS physical behavior is analyzed by means of 2D simulations. The results obtained are compared with experimental data.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131187347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A test structure for E-beam testing 电子束测试的测试结构
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292888
J. Madrenas, J. Cabestany
{"title":"A test structure for E-beam testing","authors":"J. Madrenas, J. Cabestany","doi":"10.1109/ICMTS.1993.292888","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292888","url":null,"abstract":"A structure to improve the e-beam logic testability of complex VLSI and wafer-scale integration (WSI) circuits is proposed. This structure makes possible the generation of internal logic states without any extra external connection pads by means of a low-energy and observation-compatible electron beam. Since these internal logic states reflect the presence/absence of the electron beam on a point of the IC, the beam can interact with the IC functionality. The structure is intended for CMOS technology, and is based on parasitic bipolar transistors compatible with standard CMOS processes.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129641405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An approach for relating model parameter variabilities to process fluctuations 一种将模型参数变化与过程波动联系起来的方法
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292892
J. A. Power, A. Mathewson, W. Lane
{"title":"An approach for relating model parameter variabilities to process fluctuations","authors":"J. A. Power, A. Mathewson, W. Lane","doi":"10.1109/ICMTS.1993.292892","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292892","url":null,"abstract":"A methodology that makes it possible to link circuit simulator model parameter variations and correlations to disturbances in the IC manufacturing process is presented. An example in which the variabilities among a set of 30 correlated empirical MOSFET model parameters from a 2- mu m CMOS process are represented by the variabilities of just six uncorrelated components with the aid of principal component analysis (PCA) and VARIMAX transformations is described. The derived uncorrelated components are interpreted in terms of the probable process input fluctuations causing them. These independent components may then be utilized to form the basis of realistic worst-case design methodologies or more rigorous statistical design techniques.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125362272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
SEU/SRAM as a process monitor SEU/SRAM作为过程监视器
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292893
B. Blaes, M. Buehler
{"title":"SEU/SRAM as a process monitor","authors":"B. Blaes, M. Buehler","doi":"10.1109/ICMTS.1993.292893","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292893","url":null,"abstract":"The SEU/SRAM is a 4-b static random access memory (SRAM) designed to detect single-event upsets (SEUs) produced by high energy particles. This device is used to determine the distribution in the memory cell spontaneous flip potential. The variance in this potential is determined to be due to the variation in the n-MOSFET threshold voltage. For a 1.2- mu m CMOS process, the standard deviation is found to be 8 mV. Using cumulative distribution and residual plots, stuck cells and nonnormally distributed cells are easily identified.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123478357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Limitations of electrical test information: a case study with polysilicon emitter contacts 电气测试信息的局限性:以多晶硅发射极触点为例
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292913
M. Johnson, A. Strojwas, D. Greve, R. Reuss, A. Flowers
{"title":"Limitations of electrical test information: a case study with polysilicon emitter contacts","authors":"M. Johnson, A. Strojwas, D. Greve, R. Reuss, A. Flowers","doi":"10.1109/ICMTS.1993.292913","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292913","url":null,"abstract":"It is shown in two case studies on polysilicon emitter contacts that electrical measurements are not sufficient on their own to understand observed variations in the devices under study. Combined with physical information from transmission electron microscopy (TEM) and secondary ion mass spectroscopy (SIMS) it is possible to see more clearly links between processing, structure, and electrical performance. Both interfacial oxide effects and emitter dose effects are discussed.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126595375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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