Power lateral DMOS transistor test structures

Abstract

The design and the fabrication of LDMOS test structures are discussed. The impact of cell dimensions and epilayer properties on the device characteristics is shown, together with the optimization of V/sub BR//R/sub ON/ trade-off. The influence of device layout, edge device termination and geometrical dimensions are investigated with these test structures. Square, circular, single-finger, multi-finger, and waved gate layouts are considered in the test monitor chip. The fabrication process is a conventional poly-gate double diffusion MOS (DMOS) process based on a double diffusion for the active channel formation. The resurfed LDMOS physical behavior is analyzed by means of 2D simulations. The results obtained are compared with experimental data.<>