A test structure for E-beam testing

Abstract

A structure to improve the e-beam logic testability of complex VLSI and wafer-scale integration (WSI) circuits is proposed. This structure makes possible the generation of internal logic states without any extra external connection pads by means of a low-energy and observation-compatible electron beam. Since these internal logic states reflect the presence/absence of the electron beam on a point of the IC, the beam can interact with the IC functionality. The structure is intended for CMOS technology, and is based on parasitic bipolar transistors compatible with standard CMOS processes.<>