使用低水平的预隧穿电流来表征薄氧化物的磨损和击穿

D. Dumin, J. Maddux, R. Subramoniam, R. S. Scott, D. Wong
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引用次数: 2

摘要

研究发现,通过氧化硅薄膜的低水平、预隧穿电流可以用来表征由高压应力引起的磨损。从氧化物中去除电压脉冲后产生的低电平瞬态电流被用来测量薄膜中由高压应力产生的陷阱的密度和分布。在施加压力后,流过氧化物的低水平、预隧穿电流的增加与产生的陷阱数量成正比。这种低电平电流的增加导致了一个模型的发展,该模型将高压或大电流应力期间引起的物理磨损与测量的统计时间相关的介电击穿(TDDB)分布联系起来。磨损是根据在磨损期间氧化物内部产生的陷阱来描述的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The use of low-level pre-tunneling currents to characterize thin oxide wearout and breakdown
It is found that low-level, pre-tunneling currents flowing through thin silicon oxide films can be used to characterize wearout caused by high voltage stressing. The low-level transient currents that flow after voltage pulses are removed from the oxides are used to measure the density and distribution of traps that have been generated in the films by high voltage stressing. The increase in the low-level, pre-tunneling current that flows through the oxide after the stress is directly proportional to the number of traps that have been generated. This increase in the low-level current leads to the development of a model that relates the physical wearout caused during high voltage or high current stressing to the measured statistical time dependent dielectric breakdown (TDDB) distributions. Wearout is described in terms of the traps that are generated within the oxide during wearout.<>
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