Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs)

Abstract

Wafer-level time dependent junction degradation (TDJD) is investigated as a technique for evaluating junction reliability. The TDJD phenomenon due to latent defects is revealed by high constant voltage stressing, in the same way that the TDDB test determines the long-term reliability of the junction. Latent defects enhance the junction degradation due to TDJD. Electrons trapped at the perimeter of a junction degrade junction characteristics. Although the perimeter of a junction is composed with local oxidation of silicon (LOCOS) and/or gate edge, the gate edge is found to be more significant for the TDJD characteristics.<>