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ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures最新文献

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Generic test chip formats for ASIC-oriented semiconductor process development 面向asic半导体工艺开发的通用测试芯片格式
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292911
C. Weber
{"title":"Generic test chip formats for ASIC-oriented semiconductor process development","authors":"C. Weber","doi":"10.1109/ICMTS.1993.292911","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292911","url":null,"abstract":"A novel approach towards test chip and test structure design is accelerating the introduction of application specific integrated circuit (ASIC)-oriented CMOS process generations. Specialized test chips address quality manufacturability and process integration issues within the proper time frame. Six generic test chip design formats repeat from generation to generation with scaled layout rules.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128094334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Photoemission characteristics of reverse-breakdown n/sup +/-diodes with LOCOS- and trench-isolation 具有LOCOS-和沟槽隔离的反向击穿n/sup +/-二极管的光电特性
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292924
T. Ohzone, H. Iwata
{"title":"Photoemission characteristics of reverse-breakdown n/sup +/-diodes with LOCOS- and trench-isolation","authors":"T. Ohzone, H. Iwata","doi":"10.1109/ICMTS.1993.292924","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292924","url":null,"abstract":"Photoemission-intensity profiles and photoemission images, with and without an optical filter, and anisotropic characteristics of the photon count from a reverse-biased n/sup +/-diode fabricated by local oxidation of silicon (LOCOS)- and trench-isolation are measured. Similar profiles are observed independently on the emitted photon energies. The fluctuations of the experimental results are relatively larger in trench-isolated diodes than those in LOCOS-isolated ones. The fluctuations decrease as the reverse current increases.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Direct extraction of SPICE level 3 parameters without using optimization 直接提取SPICE 3级参数，无需优化
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292902
J. Matsuda
{"title":"Direct extraction of SPICE level 3 parameters without using optimization","authors":"J. Matsuda","doi":"10.1109/ICMTS.1993.292902","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292902","url":null,"abstract":"Direct extraction methods for X/sub j/, V/sub t0/, V/sub max/ and kappa in SPICE level 3 parameters have been developed to control the parameter scatters caused by variations in the fabrication process. When using the parameter values extracted with these methods, the simulated current-voltage characteristics of a short-channel MOSFET device fit the measured ones accurately. The values obtained are almost the same as can be obtained using optimized parameter values. Since the parameter values extracted reflect the scatters directly, the methods are effective for use in such circuit designs.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131435905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluating the graft base lateral diffusion depth of high-performance bipolar transistors by using test structures 用测试结构评价高性能双极晶体管接枝基侧扩散深度
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292894
Y. Tamaki, T. Shiba, T. Kure, T. Nakamura
{"title":"Evaluating the graft base lateral diffusion depth of high-performance bipolar transistors by using test structures","authors":"Y. Tamaki, T. Shiba, T. Kure, T. Nakamura","doi":"10.1109/ICMTS.1993.292894","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292894","url":null,"abstract":"A test structure is proposed for evaluating the graft base lateral diffusion depth of high-performance double-polysilicon bipolar transistors in order to achieve high cutoff frequencies. The test structure can evaluate the effective intrinsic base width by measuring the resistance between two electrodes for several devices with different size. Graft base depth can be obtained from the active base length and the effective intrinsic base width. The graft base depths of two kinds of transistors are evaluated using the test structure. Depths of 0.05 mu m and 0.13 mu m are obtained. The maximum f/sub T/'s of these transistors are 50 GHz and 29 GHz. The feasibility of the test structure and the importance of controlling the graft base depth are confirmed through the evaluation of f/sub T/ for these transistors.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134532456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Projecting oxide lifetime by a step voltage method using electric field correction (MOS VLSI) 利用电场校正的阶跃电压法预测氧化物寿命(MOS VLSI)
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292882
T. Shigenobu, H. Uchida, N. Hirashita
{"title":"Projecting oxide lifetime by a step voltage method using electric field correction (MOS VLSI)","authors":"T. Shigenobu, H. Uchida, N. Hirashita","doi":"10.1109/ICMTS.1993.292882","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292882","url":null,"abstract":"The validity of a projection method of time dependent dielectric breakdown (TDDB) lifetime from step voltage tests is investigated. The conventional projection method is found to be unable to project correct lifetime in the intrinsic failure mode. This is caused by a decreased electric field of gate oxide due to the resistance of the gate electrode. A correction method of the electric field based on Fowler-Nordheim current transport is proposed. It yields excellent agreement between projected and measured TDDB lifetimes in all failure modes.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131764865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Metrology standards for advanced semiconductor lithography referenced to atomic spacings and geometry 参考原子间距和几何的先进半导体光刻的计量标准
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292918
E. Teague, L. W. Linholm, M. Cresswell, W. B. Penzes, J. Kramar, F. Scire, J. Villarrubia, J. Jun
{"title":"Metrology standards for advanced semiconductor lithography referenced to atomic spacings and geometry","authors":"E. Teague, L. W. Linholm, M. Cresswell, W. B. Penzes, J. Kramar, F. Scire, J. Villarrubia, J. Jun","doi":"10.1109/ICMTS.1993.292918","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292918","url":null,"abstract":"It is shown how the needs for calibrating the positional accuracy of features of an X-ray mask membrane or an optical reticle can be addressed by application of a high-accuracy coordinate metrology system known as the Molecular Measuring Machine (M-Cubed). Based on scanning tunneling microscopy and state-of-the-art heterodyne optical interferometry, the measurements of M-Cubed are referenced to fundamental standards of length and angle and with the atomic-resolution of its scanning tunneling microscope probe are validated against the interatomic spacings and geometry of single crystal surfaces. Through the use of a stable reference grid, serving as an intermediate calibration artifact, the positional accuracy of features on an X-ray mask membrane or an optical reticle can be referenced to fundamental standards of length and angle by means of the metrology system of M-Cubed.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131766262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Latch-up test structures for reliability analysis of a floating well based smart power technology 基于智能电源技术的浮式井可靠性分析锁存测试结构
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292885
M. Puig Vidal, M. Bafleur, J. Buxo, G. Sarrabayrouse
{"title":"Latch-up test structures for reliability analysis of a floating well based smart power technology","authors":"M. Puig Vidal, M. Bafleur, J. Buxo, G. Sarrabayrouse","doi":"10.1109/ICMTS.1993.292885","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292885","url":null,"abstract":"Self-isolated CMOS double-diffusion MOS (DMOS) technology is a cost effective smart power technology. It is shown that, using a floating well concept as latch-up protection, self-isolated CMOS/DMOS technology can be made cost effective and reliable. The reliability of this concept is demonstrated as far as both static and dynamic latch-up is concerned, as well as with regard to MOS transistor performance.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117133400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling and characterization of MOSFET width dependencies MOSFET宽度依赖性的建模和表征
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292881
R. Ashton, P. Layman, C. McAndrew
{"title":"Modeling and characterization of MOSFET width dependencies","authors":"R. Ashton, P. Layman, C. McAndrew","doi":"10.1109/ICMTS.1993.292881","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292881","url":null,"abstract":"An improved model of MOSFET behavior over width is presented, together with a new, simple, and robust method to determine MOSFET width parameters from measurement data using nonlinear optimization. The authors' model properly accounts for the variation of effective channel width, series resistance, and threshold voltage with masked channel width and gate bias, and determines all MOSFET width parameters in a consistent manner. Details of test structures used for MOSFET width characterization are given.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126689684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Measurement of minimum line widths using Fallon ladders 用法伦梯测量最小线宽
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292909
M. Fallon, A. Walton
{"title":"Measurement of minimum line widths using Fallon ladders","authors":"M. Fallon, A. Walton","doi":"10.1109/ICMTS.1993.292909","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292909","url":null,"abstract":"A test structure is proposed to assess resolution both optically and electrically. The structure consists of a ladder of conductors with incrementally varied widths. The maximum resolution can be assessed by either measuring the resistance or counting the rungs that have been resolved. The results indicate a plateau from zero towards a negative value of focus offset. There is a sharp resolution reduction as the stepper focus is increased above the nominal focus setting. The electrical measurements correlate well with scanning electron microscopy (SEM) results, and prove to be considerably faster, while removing subjectivity from the measurements. It is shown that the change in resistance of the Fallon ladder as resolution decreases is sensitive enough to enable this technique to be applicable to current processes.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127268439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The use of test structures to identify leakage failure mechanisms in CMOS inputs 使用测试结构来识别CMOS输入的泄漏失效机制
ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures Pub Date : 1993-03-22 DOI: 10.1109/ICMTS.1993.292884
J. Orchard-Webb
{"title":"The use of test structures to identify leakage failure mechanisms in CMOS inputs","authors":"J. Orchard-Webb","doi":"10.1109/ICMTS.1993.292884","DOIUrl":"https://doi.org/10.1109/ICMTS.1993.292884","url":null,"abstract":"An input structure is dissected into simple components and into combinations of components, and is processed so that the device performance under stress can be clearly understood. The study of leakage currents in these structures is then used to identify the location and cause of leakage in a complete device. The failure mechanism is shown to be caused by inversion at the edge of the n/sup +/V/sub dd/ connection of the thick oxide protection diode.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125214310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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