Latch-up test structures for reliability analysis of a floating well based smart power technology

Abstract

Self-isolated CMOS double-diffusion MOS (DMOS) technology is a cost effective smart power technology. It is shown that, using a floating well concept as latch-up protection, self-isolated CMOS/DMOS technology can be made cost effective and reliable. The reliability of this concept is demonstrated as far as both static and dynamic latch-up is concerned, as well as with regard to MOS transistor performance.<>