M. Puig Vidal, M. Bafleur, J. Buxo, G. Sarrabayrouse
{"title":"基于智能电源技术的浮式井可靠性分析锁存测试结构","authors":"M. Puig Vidal, M. Bafleur, J. Buxo, G. Sarrabayrouse","doi":"10.1109/ICMTS.1993.292885","DOIUrl":null,"url":null,"abstract":"Self-isolated CMOS double-diffusion MOS (DMOS) technology is a cost effective smart power technology. It is shown that, using a floating well concept as latch-up protection, self-isolated CMOS/DMOS technology can be made cost effective and reliable. The reliability of this concept is demonstrated as far as both static and dynamic latch-up is concerned, as well as with regard to MOS transistor performance.<<ETX>>","PeriodicalId":123048,"journal":{"name":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Latch-up test structures for reliability analysis of a floating well based smart power technology\",\"authors\":\"M. Puig Vidal, M. Bafleur, J. Buxo, G. Sarrabayrouse\",\"doi\":\"10.1109/ICMTS.1993.292885\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Self-isolated CMOS double-diffusion MOS (DMOS) technology is a cost effective smart power technology. It is shown that, using a floating well concept as latch-up protection, self-isolated CMOS/DMOS technology can be made cost effective and reliable. The reliability of this concept is demonstrated as far as both static and dynamic latch-up is concerned, as well as with regard to MOS transistor performance.<<ETX>>\",\"PeriodicalId\":123048,\"journal\":{\"name\":\"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1993.292885\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1993.292885","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Latch-up test structures for reliability analysis of a floating well based smart power technology
Self-isolated CMOS double-diffusion MOS (DMOS) technology is a cost effective smart power technology. It is shown that, using a floating well concept as latch-up protection, self-isolated CMOS/DMOS technology can be made cost effective and reliable. The reliability of this concept is demonstrated as far as both static and dynamic latch-up is concerned, as well as with regard to MOS transistor performance.<>