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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)最新文献

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Mobility enhancement in strained Si NMOSFETs with HfO/sub 2/ gate dielectrics HfO/sub /栅极介质增强应变Si nmosfet的迁移率
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015368
K. Rim, E. Gusev, C. D'Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B. Lee, A. Mocuta, J. Welser, S. Cohen, M. Leong, H.-S.P. Wong
{"title":"Mobility enhancement in strained Si NMOSFETs with HfO/sub 2/ gate dielectrics","authors":"K. Rim, E. Gusev, C. D'Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B. Lee, A. Mocuta, J. Welser, S. Cohen, M. Leong, H.-S.P. Wong","doi":"10.1109/VLSIT.2002.1015368","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015368","url":null,"abstract":"Integration of strained Si and high-K gate dielectric is demonstrated for the first time. While providing a >1000/spl times/ gate leakage reduction, strained Si NMOSFETs with HfO/sub 2/ gate dielectric exhibit 60% higher mobility than the unstrained Si device with HfO/sub 2/ gate dielectrics, and 30% higher mobility than the conventional Si NMOSFETs with SiO/sub 2/ gate dielectric (universal MOSFET mobility).","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127640574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
<100> channel strained-SiGe p-MOSFET with enhanced hole mobility and lower parasitic resistance 沟道应变- sige p-MOSFET具有增强的空穴迁移率和更低的寄生电阻
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015403
M. Shima, T. Ueno, T. Kumise, H. Shido, Y. Sakuma, S. Nakamura
{"title":"<100> channel strained-SiGe p-MOSFET with enhanced hole mobility and lower parasitic resistance","authors":"M. Shima, T. Ueno, T. Kumise, H. Shido, Y. Sakuma, S. Nakamura","doi":"10.1109/VLSIT.2002.1015403","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015403","url":null,"abstract":"Employment of <100> channel direction in a strained-Si/sub 0.8/Ge/sub 0.2/ p-MOSFET has demonstrated the substantial amount of hole mobility enhancement as large as 25% and parasitic resistance reduction of 20% compared to a <110> strained-Si/sub 0.8/Ge/sub 0.2/ Channel p-MOSFET, which already has an advantage in mobility and the threshold voltage roll-off characteristic over the Si p-MOSFET. This result indicates that the <100> strained SiGe channel p-MOSFET is a promising and practical candidate for realizing high-speed CMOS devices under low-voltage operation.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123249331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Extended 0.13 /spl mu/m CMOS technology for the ultra high-speed and MS/RF application segments 为超高速和MS/RF应用领域扩展了0.13 /spl mu/m CMOS技术
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015391
C. Chang, C. Chao, Y. Leung, C. Lin, H. Hsu, Y.P. Wang, S.Y. Chang, T. Chiu, J. Shyu, C.C. Wu, C. Wang, R. Chang, C.W. Chen, C.F. Huang, C. Chen, S.H. Chen, T. Yeh, J.Y. Cheng, J. Liaw, Y. Chu, T. Ong, M.C. Yu, C. Yu, H.J. Lin, H. Tao, M. Liang, Y. See, C. H. Diaz, Y.C. Sun
{"title":"Extended 0.13 /spl mu/m CMOS technology for the ultra high-speed and MS/RF application segments","authors":"C. Chang, C. Chao, Y. Leung, C. Lin, H. Hsu, Y.P. Wang, S.Y. Chang, T. Chiu, J. Shyu, C.C. Wu, C. Wang, R. Chang, C.W. Chen, C.F. Huang, C. Chen, S.H. Chen, T. Yeh, J.Y. Cheng, J. Liaw, Y. Chu, T. Ong, M.C. Yu, C. Yu, H.J. Lin, H. Tao, M. Liang, Y. See, C. H. Diaz, Y.C. Sun","doi":"10.1109/VLSIT.2002.1015391","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015391","url":null,"abstract":"This paper introduces new technology features to support ultra high-speed and MS/RF applications incorporated into a leading-edge fully manufacturable 0.13 /spl mu/m CMOS foundry technology (K.K. Young et al, IEDM Tech Digest, pp. 563-566, 2000). New core devices with 15.5 /spl Aring/ and nominal 75 nm physical gate lengths support at least 10% performance improvement with respect to prior release. These devices offer the best I/sub off/-I/sub dsat/ performance reported so far for 1.2 V applications. To support high-speed I/O standards, additional 1.8 V-32 /spl Aring/ I/O devices are integrated with the 15.5 /spl Aring/ transistors. Leading-edge passive elements for MS/RF applications are reported in this work. Advanced Cu/low-k back end process integration that can support up to nine layers of metal is also demonstrated.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"61 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116421475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate 使用薄膜绝缘体上硅基板的应变soi mosfet的高性能CMOS操作
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015410
T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, S. Takagi
{"title":"High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate","authors":"T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, S. Takagi","doi":"10.1109/VLSIT.2002.1015410","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015410","url":null,"abstract":"We demonstrate high performance CMOS operation of fully depleted (FD) and partially depleted (PD) strained-SOI MOSFETs on a new thin-film-SGOI substrate with high Ge content (25%) fabricated by the combination of SIMOX and ITOX technologies, without using the usual thick SiGe buffer layers. We verify high electron (85%) and hole (50%) mobility enhancement of strained-SOI MOSFETs against the universal carrier mobility. It is demonstrated, as a result, that the gate delay time of strained-SOI CMOS is improved by about 70%, compared to that of control-SOI CMOS. Moreover, we also discuss both the strained-Si thickness and the effective field dependent difference between electron and hole mobility enhancement factors of strained-SOI CMOS.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation 低待机功率CMOS与HfO/sub 2/栅极氧化物为100纳米一代
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015375
S. Pidin, Y. Morisaki, Y. Sugita, T. Aoyama, K. Irino, T. Nakamura, T. Sugii
{"title":"Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation","authors":"S. Pidin, Y. Morisaki, Y. Sugita, T. Aoyama, K. Irino, T. Nakamura, T. Sugii","doi":"10.1109/VLSIT.2002.1015375","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015375","url":null,"abstract":"We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO/sub 2/ gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). A conventional CMOS process was used with high-temperature S/D anneal of /spl ges/1000/spl deg/C, cobalt-silicide and pocket implants. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121148082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
35 nm CMOS FinFETs 35纳米CMOS finfet
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015409
Fu-Liang Yang, Haur-Ywh Chen, Fang-Cheng Chen, Y. Chan, Kuo-Nan Yang, Chih-Jian Chen, H. Tao, Yang-Kyu Choi, M. Liang, C. Hu
{"title":"35 nm CMOS FinFETs","authors":"Fu-Liang Yang, Haur-Ywh Chen, Fang-Cheng Chen, Y. Chan, Kuo-Nan Yang, Chih-Jian Chen, H. Tao, Yang-Kyu Choi, M. Liang, C. Hu","doi":"10.1109/VLSIT.2002.1015409","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015409","url":null,"abstract":"We demonstrate for the first time high performance 35 nm CMOS FinFETs. Symmetrical NFET and PFET off-state leakage is realized with a simple technology. For 1 volt operation at a conservative 24 /spl Aring/ gate oxide thickness, the transistors give drive currents of 1240 /spl mu/A//spl mu/m for NFET and 500 /spl mu/A//spl mu/m for PFET at an off current of 200 nA//spl mu/m. Excellent hot carrier immunity is achieved. Device performance parameters exceed ITRS projections.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129741572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
An ultra-thin silicon nitride gate dielectric with oxygen-enriched interface (OI-SiN) for CMOS with EOT of 0.9 nm and beyond 具有富氧界面(OI-SiN)的超薄氮化硅栅极电介质，用于EOT为0.9 nm及以上的CMOS
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015453
S. Tsujikawa, T. Mine, Y. Shimamoto, O. Tonomura, R. Tsuchiya, K. Ohnishi, H. Hamamura, K. Torii, T. Onai, J. Yugami
{"title":"An ultra-thin silicon nitride gate dielectric with oxygen-enriched interface (OI-SiN) for CMOS with EOT of 0.9 nm and beyond","authors":"S. Tsujikawa, T. Mine, Y. Shimamoto, O. Tonomura, R. Tsuchiya, K. Ohnishi, H. Hamamura, K. Torii, T. Onai, J. Yugami","doi":"10.1109/VLSIT.2002.1015453","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015453","url":null,"abstract":"We demonstrate a SiN gate dielectric with oxygen-enriched interface (OI-SiN). A process in which oxygen atoms are incorporated after forming SiN provides enhanced nitrogen concentration and oxygen-enriched interface simultaneously even in the region of EOT < 1.5 nm. Thus we developed an OI-SiN gate dielectric with EOT of 0.9 nm that brought about low gate leakage current, good interface properties and excellent resistance to boron penetration.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129083216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Improved thermal stability and device performance of ultra-thin (EOT<10 /spl Aring/) gate dielectric MOSFETs by using hafnium oxynitride (HfO/sub x/N/sub y/) 氮化铪(HfO/sub x/N/sub y/)改善超薄(EOT<10 /spl Aring/)栅极介电mosfet的热稳定性和器件性能
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015427
C. Kang, H. Cho, K. Onishi, R. Choi, R. Nieh, S. Goplan, S. Krishnan, J.C. Lee
{"title":"Improved thermal stability and device performance of ultra-thin (EOT<10 /spl Aring/) gate dielectric MOSFETs by using hafnium oxynitride (HfO/sub x/N/sub y/)","authors":"C. Kang, H. Cho, K. Onishi, R. Choi, R. Nieh, S. Goplan, S. Krishnan, J.C. Lee","doi":"10.1109/VLSIT.2002.1015427","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015427","url":null,"abstract":"Hafnium oxynitride (HfO/sub x/N/sub y/) film was prepared and characterized for gate dielectrics application with EOT<10 /spl Aring/ for the first time. Thermal stability and crystallization during the subsequent thermal process were improved significantly by using HfO/sub x/N/sub y/ over HfO/sub 2/. Furthermore, excellent transistor characteristics were obtained for both p and nMOSFETs.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect UX6-100纳米一代CMOS集成技术，具有Cu/低k互连
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015389
K. Fukasaku, A. Ono, T. Hirai, Y. Yasuda, N. Okada, S. Koyama, T. Tamura, Y. Yamada, T. Nakata, M. Yamana, N. Ikezawa, T. Matsuda, K. Arita, H. Nambu, A. Nishizawa, K. Nakabeppu, N. Nakamura
{"title":"UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect","authors":"K. Fukasaku, A. Ono, T. Hirai, Y. Yasuda, N. Okada, S. Koyama, T. Tamura, Y. Yamada, T. Nakata, M. Yamana, N. Ikezawa, T. Matsuda, K. Arita, H. Nambu, A. Nishizawa, K. Nakabeppu, N. Nakamura","doi":"10.1109/VLSIT.2002.1015389","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015389","url":null,"abstract":"UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128129210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology 将高性能、低泄漏和混合信号特性集成到100纳米CMOS技术中
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015388
T. Schafbauer, J. Brighten, Yi-Cheng Chen, L. Clevenger, M. Commons, A. Cowley, K. Esmark, A. Grassmann, U. Hodel, Hsiang-Jen Huang, Shih-Fen Huang, Yimin Huang, E. Kaltalioglu, G. Knoblinger, Ming-Tsan Lee, A. Leslie, P. Leung, Baozhen Li, Chuan Lin, Yi-Hsiung Lin, W. Nissl, P. Nguyen, A. Olbrich, P. Riess, N. Rovedo, S. Sportouch, A. Thomas, D. Vietzke, M. Wendel, R. Wong, Q. Ye, K. Lin, T. Schiml, C. Wann
{"title":"Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology","authors":"T. Schafbauer, J. Brighten, Yi-Cheng Chen, L. Clevenger, M. Commons, A. Cowley, K. Esmark, A. Grassmann, U. Hodel, Hsiang-Jen Huang, Shih-Fen Huang, Yimin Huang, E. Kaltalioglu, G. Knoblinger, Ming-Tsan Lee, A. Leslie, P. Leung, Baozhen Li, Chuan Lin, Yi-Hsiung Lin, W. Nissl, P. Nguyen, A. Olbrich, P. Riess, N. Rovedo, S. Sportouch, A. Thomas, D. Vietzke, M. Wendel, R. Wong, Q. Ye, K. Lin, T. Schiml, C. Wann","doi":"10.1109/VLSIT.2002.1015388","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015388","url":null,"abstract":"Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128440067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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