2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)最新文献_第7页

High-performance strained Si-on-insulator MOSFETs by novel fabrication processes utilizing Ge-condensation technique 利用ge -冷凝技术制备高性能应变绝缘体硅基mosfet

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015405

T. Tezuka, N. Sugiyama, T. Mizuno, S. Takagi

引用次数: 26

Novel integration technologies for highly manufacturable 32 Mb FRAM 用于高度可制造的32 Mb FRAM的新颖集成技术

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015456

H.H. Kim, Y.J. Song, S.Y. Lee, H. Joo, N. Jang, D. Jung, Y.S. Park, S.O. Park, K.M. Lee, S. Joo, S.W. Lee, S. Nam, K. Kim

{"title":"Novel integration technologies for highly manufacturable 32 Mb FRAM","authors":"H.H. Kim, Y.J. Song, S.Y. Lee, H. Joo, N. Jang, D. Jung, Y.S. Park, S.O. Park, K.M. Lee, S. Joo, S.W. Lee, S. Nam, K. Kim","doi":"10.1109/VLSIT.2002.1015456","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015456","url":null,"abstract":"Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125121474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Novel resist pattern transfer process for 70 nm technology node using 157-nm lithography 采用157nm光刻技术的70nm工艺节点抗蚀图案转移新工艺

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015451

S. Miyoshi, T. Furukawa, H. Watanabe, S. Irie, T. Itani

引用次数: 4

A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications 100纳米CMOS技术，具有“侧壁缺口”40纳米晶体管和sic封顶的Cu/VLK互连，适用于高性能微处理器应用

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015390

S. Nakai, Y. Takao, S. Otsuka, K. Sugiyama, H. Ohta, A. Yamanoue, Y. Iriyama, R. Nanjyo, S. Sekino, H. Nagai, K. Naitoh, R. Nakamura, Y. Sambonsugi, Y. Tagawa, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, S. Sugatani, T. Sugii, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, I. Hanyu, K. Yanai

{"title":"A 100 nm CMOS technology with \"sidewall-notched\" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications","authors":"S. Nakai, Y. Takao, S. Otsuka, K. Sugiyama, H. Ohta, A. Yamanoue, Y. Iriyama, R. Nanjyo, S. Sekino, H. Nagai, K. Naitoh, R. Nakamura, Y. Sambonsugi, Y. Tagawa, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, S. Sugatani, T. Sugii, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, I. Hanyu, K. Yanai","doi":"10.1109/VLSIT.2002.1015390","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015390","url":null,"abstract":"A 40 nm CMOS transistor, an ultra high density 6T SRAM cell, and 10-level Cu interconnects and very-low-k (VLK) dielectrics for high performance microprocessor applications are presented. Key process features are the following: (1) High-NA 193 nm photolithography with phase shift mask and optical proximity correction (OPC) allows 40 nm gate length and the smallest 6T SRAM cell (<1 /spl mu/m/sup 2/). (2) A unique transistor feature which is referred to as \"sidewall-notched gate\" enables an optimal pocket implant placement and suppresses variations of the notch width much better than poly-notched gate structure. (3) 1.1 nm nitrided oxide (1.9 nm inversion T/sub ox/) is used to achieve high drive current, and the thermal budget is reduced to suppress the boron penetration. (4) SiC-capped Cu/SiLK structure in 0.28 /spl mu/m pitch metal 1-4 layers realizes k/sub eff/ of 3.0.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115200569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Reliability projection and polarity dependence of TDDB for ultra thin CVD HfO/sub 2/ gate dielectrics 超薄CVD HfO/sub / gate电介质TDDB的可靠性投影及极性依赖性

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015397

S.J. Lee, S. Rhee, R. Clark, D. Kwong

引用次数: 22

High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors 高性能60纳米CMOS技术，增强了BST(体微束缚)结构SOI和微处理器的Cu/low-k (k=2.9)互连

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015436

I. Kudo, S. Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou, T. Tanaka, T. Matuda, M. Ikeda, K. Imai, H. Ooka

引用次数: 1

Advanced CMOS transistors with a novel HfSiON gate dielectric 具有新型HfSiON栅介质的先进CMOS晶体管

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015428

A. Rotondaro, M. Visokay, J. J. Chambers, A. Shanware, R. Khamankar, H. Bu, R. Laaksonen, L. Tsung, M. Douglas, R. Kuan, M. Bevan, T. Grider, J. McPherson, L. Colombo

引用次数: 62

Supply voltage strategies for minimizing the power of CMOS processors 降低CMOS处理器功耗的电源电压策略

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015408

Jin Cai, Y. Taur, Shih-Fen Huang, D. Frank, S. Kosonocky, R. Dennard

引用次数: 15

Integration of high performance dual workfunction logic CMOS transistors with a dense 8F/sup 2/ vertical DRAM cell 集成高性能双工作功能逻辑CMOS晶体管与密集的8F/sup 2/垂直DRAM单元

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015387

R. Rengarajan, R. Malik, Haining Yang, W. Yan, R. Ramachandran, Boyong He, R. Divakaruni, Yujun Li

引用次数: 1

Soft error rate scaling for emerging SOI technology options 新兴SOI技术选项的软错误率缩放

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI: 10.1109/VLSIT.2002.1015382

P. Oldiges, K. Bernstein, D. Heidel, B. Klaasen, E. Cannon, R. Dennard, H. Tang, M. Ieong, H.-S.P. Wong

引用次数: 30