Supply voltage strategies for minimizing the power of CMOS processors

Abstract

This paper presents a dual supply voltage strategy for reduction of the total (static and dynamic) power of high performance CMOS processors. By expressing CMOS delay, static power, and dynamic power in terms of the power supply voltage V/sub DD/ and threshold voltage V/sub T/, an optimization procedure that takes the circuit activity factor into account is performed to find the V/sub DD/ and V/sub T/ for minimum total power at given performance levels. It is shown that 50% power reduction or 20% performance enhancement can be attained by adopting both a low (0.5 V) supply voltage for high-activity circuits and a high (1.2 V) supply voltage for low-activity circuits in a 100 nm-node CMOS technology.