High-performance strained Si-on-insulator MOSFETs by novel fabrication processes utilizing Ge-condensation technique

Abstract

Strained SOI (SSOI)-nMOSFETs with enhanced mobility up to 67% were fabricated on a strain-relaxed SiGe-on-insulator substrate using a novel Ge-condensation technique. This method, using only standard Si processes, realizes smooth SSOI surfaces without using SIMOX, wafer bonding, surface polishing or any other special processes. Relaxation ratio of the SiGe substrate was varied from 0% to 100%, resulting in the control of threshold voltage. The Ge-condensation process using conventional SOI substrates is an attractive technique for fabrication of multi-threshold SSOI-CMOS circuits with high current drive.