高性能60纳米CMOS技术，增强了BST(体微束缚)结构SOI和微处理器的Cu/low-k (k=2.9)互连

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015436

I. Kudo, S. Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou, T. Tanaka, T. Matuda, M. Ikeda, K. Imai, H. Ooka

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引用次数: 1

摘要

我们开发了用于微处理器产品的高性能/低有功功率CMOS技术。其特点是:(1)采用高剂量低能离子注入(I/I)实现S/D扩展的驱动电流增强，(2)采用部分沟槽隔离和局部通道掺杂的体微束缚(BST) CMOS/SOI，(3)采用低k (k=2.9)介电介质的Cu互连。

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High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors

We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.

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来源期刊

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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