S. Pidin, Y. Morisaki, Y. Sugita, T. Aoyama, K. Irino, T. Nakamura, T. Sugii
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引用次数: 18
Abstract
We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO/sub 2/ gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). A conventional CMOS process was used with high-temperature S/D anneal of /spl ges/1000/spl deg/C, cobalt-silicide and pocket implants. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.