低待机功率CMOS与HfO/sub 2/栅极氧化物为100纳米一代

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015375

S. Pidin, Y. Morisaki, Y. Sugita, T. Aoyama, K. Irino, T. Nakamura, T. Sugii

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引用次数: 18

摘要

采用原子层沉积法(ALD)制备了物理厚度为3nm的HfO/sub - 2/栅极介质，制备了55 nm的多晶硅门控n-和p- mosfet。采用传统的CMOS工艺，采用/spl /1000/spl℃高温S/D退火，硅化钴和口袋植入物。由于极漏电流的大幅降低，该器件在低待机功率应用中表现出非常有希望的特性。

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Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation

We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO/sub 2/ gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). A conventional CMOS process was used with high-temperature S/D anneal of /spl ges/1000/spl deg/C, cobalt-silicide and pocket implants. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.

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来源期刊

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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