35纳米CMOS finfet

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015409

Fu-Liang Yang, Haur-Ywh Chen, Fang-Cheng Chen, Y. Chan, Kuo-Nan Yang, Chih-Jian Chen, H. Tao, Yang-Kyu Choi, M. Liang, C. Hu

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引用次数: 42

摘要

我们首次展示了高性能的35纳米CMOS finfet。用简单的技术实现了非场效应晶体管和非场效应晶体管的对称失态泄漏。在保守的24 /spl栅极氧化物厚度下，1伏特工作时，晶体管的驱动电流为1240 /spl mu/ a //spl mu/m，在关闭电流为200 nA//spl mu/m时，fet的驱动电流为500 /spl mu/ a //spl mu/m。实现了出色的热载体免疫。设备性能参数超过ITRS预测。

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35 nm CMOS FinFETs

We demonstrate for the first time high performance 35 nm CMOS FinFETs. Symmetrical NFET and PFET off-state leakage is realized with a simple technology. For 1 volt operation at a conservative 24 /spl Aring/ gate oxide thickness, the transistors give drive currents of 1240 /spl mu/A//spl mu/m for NFET and 500 /spl mu/A//spl mu/m for PFET at an off current of 200 nA//spl mu/m. Excellent hot carrier immunity is achieved. Device performance parameters exceed ITRS projections.

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2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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