High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate

Abstract

We demonstrate high performance CMOS operation of fully depleted (FD) and partially depleted (PD) strained-SOI MOSFETs on a new thin-film-SGOI substrate with high Ge content (25%) fabricated by the combination of SIMOX and ITOX technologies, without using the usual thick SiGe buffer layers. We verify high electron (85%) and hole (50%) mobility enhancement of strained-SOI MOSFETs against the universal carrier mobility. It is demonstrated, as a result, that the gate delay time of strained-SOI CMOS is improved by about 70%, compared to that of control-SOI CMOS. Moreover, we also discuss both the strained-Si thickness and the effective field dependent difference between electron and hole mobility enhancement factors of strained-SOI CMOS.