K. Fukasaku, A. Ono, T. Hirai, Y. Yasuda, N. Okada, S. Koyama, T. Tamura, Y. Yamada, T. Nakata, M. Yamana, N. Ikezawa, T. Matsuda, K. Arita, H. Nambu, A. Nishizawa, K. Nakabeppu, N. Nakamura
{"title":"UX6-100纳米一代CMOS集成技术，具有Cu/低k互连","authors":"K. Fukasaku, A. Ono, T. Hirai, Y. Yasuda, N. Okada, S. Koyama, T. Tamura, Y. Yamada, T. Nakata, M. Yamana, N. Ikezawa, T. Matsuda, K. Arita, H. Nambu, A. Nishizawa, K. Nakabeppu, N. Nakamura","doi":"10.1109/VLSIT.2002.1015389","DOIUrl":null,"url":null,"abstract":"UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect\",\"authors\":\"K. Fukasaku, A. Ono, T. Hirai, Y. Yasuda, N. Okada, S. Koyama, T. Tamura, Y. Yamada, T. Nakata, M. Yamana, N. Ikezawa, T. Matsuda, K. Arita, H. Nambu, A. Nishizawa, K. Nakabeppu, N. Nakamura\",\"doi\":\"10.1109/VLSIT.2002.1015389\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015389\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015389","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect
UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.
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