UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect

Abstract

UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.