使用薄膜绝缘体上硅基板的应变soi mosfet的高性能CMOS操作

T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, S. Takagi
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引用次数: 24

摘要

我们展示了完全耗尽(FD)和部分耗尽(PD)应变soi mosfet在SIMOX和ITOX技术组合制造的具有高Ge含量(25%)的新型薄膜sgoi衬底上的高性能CMOS操作,而无需使用通常的厚SiGe缓冲层。我们验证了应变soi mosfet对通用载流子迁移率的高电子(85%)和空穴(50%)迁移率增强。结果表明,与控制型soi CMOS相比,应变型soi CMOS的栅延迟时间提高了约70%。此外,我们还讨论了应变si厚度以及应变soi CMOS的电子和空穴迁移率增强因子之间的有效场依赖差。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate
We demonstrate high performance CMOS operation of fully depleted (FD) and partially depleted (PD) strained-SOI MOSFETs on a new thin-film-SGOI substrate with high Ge content (25%) fabricated by the combination of SIMOX and ITOX technologies, without using the usual thick SiGe buffer layers. We verify high electron (85%) and hole (50%) mobility enhancement of strained-SOI MOSFETs against the universal carrier mobility. It is demonstrated, as a result, that the gate delay time of strained-SOI CMOS is improved by about 70%, compared to that of control-SOI CMOS. Moreover, we also discuss both the strained-Si thickness and the effective field dependent difference between electron and hole mobility enhancement factors of strained-SOI CMOS.
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