T. Schafbauer, J. Brighten, Yi-Cheng Chen, L. Clevenger, M. Commons, A. Cowley, K. Esmark, A. Grassmann, U. Hodel, Hsiang-Jen Huang, Shih-Fen Huang, Yimin Huang, E. Kaltalioglu, G. Knoblinger, Ming-Tsan Lee, A. Leslie, P. Leung, Baozhen Li, Chuan Lin, Yi-Hsiung Lin, W. Nissl, P. Nguyen, A. Olbrich, P. Riess, N. Rovedo, S. Sportouch, A. Thomas, D. Vietzke, M. Wendel, R. Wong, Q. Ye, K. Lin, T. Schiml, C. Wann
{"title":"将高性能、低泄漏和混合信号特性集成到100纳米CMOS技术中","authors":"T. Schafbauer, J. Brighten, Yi-Cheng Chen, L. Clevenger, M. Commons, A. Cowley, K. Esmark, A. Grassmann, U. Hodel, Hsiang-Jen Huang, Shih-Fen Huang, Yimin Huang, E. Kaltalioglu, G. Knoblinger, Ming-Tsan Lee, A. Leslie, P. Leung, Baozhen Li, Chuan Lin, Yi-Hsiung Lin, W. Nissl, P. Nguyen, A. Olbrich, P. Riess, N. Rovedo, S. Sportouch, A. Thomas, D. Vietzke, M. Wendel, R. Wong, Q. Ye, K. Lin, T. Schiml, C. Wann","doi":"10.1109/VLSIT.2002.1015388","DOIUrl":null,"url":null,"abstract":"Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology\",\"authors\":\"T. Schafbauer, J. Brighten, Yi-Cheng Chen, L. Clevenger, M. Commons, A. Cowley, K. Esmark, A. Grassmann, U. Hodel, Hsiang-Jen Huang, Shih-Fen Huang, Yimin Huang, E. Kaltalioglu, G. Knoblinger, Ming-Tsan Lee, A. Leslie, P. Leung, Baozhen Li, Chuan Lin, Yi-Hsiung Lin, W. Nissl, P. Nguyen, A. Olbrich, P. Riess, N. Rovedo, S. Sportouch, A. Thomas, D. Vietzke, M. Wendel, R. Wong, Q. Ye, K. Lin, T. Schiml, C. Wann\",\"doi\":\"10.1109/VLSIT.2002.1015388\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015388\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015388","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology
Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.
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