2020 IEEE Symposium on VLSI Technology最新文献_第8页

Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node 超过7nm节点的CMOS技术实现多vt器件缩放

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265050

V. Chang, S.H. Wang, J. Lu, W. Wu, B. Wu, B. Hsu, K. Kwong, J. Yeh, C. Chang, C.H. Chen, C. O. Chui, M. Yeh, K.B. Huang, R. Chen, K.S. Chen, S. Wu

引用次数: 5

Flexible and Transparent BEOL Monolithic 3DIC Technology for Human Skin Adaptable Internet of Things Chips 灵活透明的BEOL单片3DIC人体皮肤适应性物联网芯片

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265079

M. Kao, Wei-Hsiang Chen, Po-Cheng Hou, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh

引用次数: 0

Silicon is Greener: Why Innovation in Circuits is Needed for Sustainability 硅更环保:为什么电路创新需要可持续发展

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265102

J. Lloyd, Niall Kearney, C. Lyden, Damien McCartney, David Robertson, Meabh Shine

引用次数: 0

Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs 热电子是亚5nm HZO效应场效应管的主要退化源

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265067

A. Tan, M. Pešić, L. Larcher, Y. Liao, Li-Chen Wang, J. Bae, C. Hu, S. Salahuddin

引用次数: 24

Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry 可解释的神经网络模拟和减少FinFET电路的自热

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265107

Chia-Che Chung, Hsin-Cheng Lin, H. H. Lin, W. K. Wan, M. Yang, C. Liu

引用次数: 2

A Monolithic 3D Integration of RRAM Array with Oxide Semiconductor FET for In-memory Computing in Quantized Neural Network AI Applications 用于量化神经网络人工智能内存计算的RRAM阵列与氧化半导体场效应管的单片三维集成

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265062

Jixuan Wu, Fei Mo, T. Saraya, T. Hiramoto, M. Kobayashi

引用次数: 18

Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM with 10 ns Low Power Write Operation, 10 years Retention and Endurance $> 10^{11}$ 四接口p-MTJ在1X nm STT-MRAM上的可扩展性，10 ns低功耗写操作，10年保留和寿命$> 10^{11}$

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265104

S. Miura, K. Nishioka, H. Naganuma, T. V. A. Nguyen, H. Honjo, S. Ikeda, T. Watanabe, H. Inoue, M. Niwa, T. Tanigawa, Y. Noguchi, T. Yoshiduka, M. Yasuhira, T. Endoh

{"title":"Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM with 10 ns Low Power Write Operation, 10 years Retention and Endurance $> 10^{11}$","authors":"S. Miura, K. Nishioka, H. Naganuma, T. V. A. Nguyen, H. Honjo, S. Ikeda, T. Watanabe, H. Inoue, M. Niwa, T. Tanigawa, Y. Noguchi, T. Yoshiduka, M. Yasuhira, T. Endoh","doi":"10.1109/VLSITechnology18217.2020.9265104","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265104","url":null,"abstract":"We have firstly fabricated quad-interface perpendicular MTJ (Quad-MTJ) down to 33 nm with our developed PVD, RIE and damage control integration process technologies under 300 mm process. Secondly, we demonstrated scalability merit as well as high speed writing of Quad-MTJ compared with double-interface p-MTJ (Double-MTJ) as follows; (a) two times larger thermal stability factor $Delta(1mathrm{X}$ nm Quad- MTJ is extrapolated to achieve 10 years retention.), (b) lower write voltage at short write pulse regions at less than 30 ns, (c) in scaled MTJ, effective suppression of write current increase for higher write speed, (d) more than 2 times higher write efficiency at 10ns write operation down to 33 nm MTJ. Finally, we revealed that our developed 33 nm Quad-MTJ achieve excellent endurance of more 1011 thanks to higher write efficiency and low damage integration process technology. These results show that the Quad-MTJ technology is one of promising way for low power, high speed and enough reliable STT -MRAM with excellent scalability down to 1X nm node.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"57 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84341340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

High-Temperature Operation of Chip-Scale Silicon-Photonic Transceiver 芯片级硅光子收发器的高温工作

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265051

D. Okamoto, Y. Suzuki, J. Fujikata, M. Tokushima, J. Ushida, T. Horikawa, K. Takemura, T. Nakamura, Y. Hagihara, K. Yashiki, M. Kurihara, K. Kinoshita, K. Kurata

引用次数: 0

Proposal and Experimental Demonstration of Reservoir Computing using Hf0.5Zr0.5O2/Si FeFETs for Neuromorphic Applications 神经形态应用Hf0.5Zr0.5O2/Si效应场效应油藏计算的提出与实验论证

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265110

E. Nako, K. Toprasertpong, R. Nakane, Z. Wang, Y. Miyatake, M. Takenaka, S. Takagi

引用次数: 17

Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing 28nm FD-SOI技术在低至100mK低温下的量子计算变异性评估

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265034

B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen, R. Maurand, S. Haendler, A. Juge, E. Vincent, P. Galy, G. Ghibaudo, M. Vinet, S. de Franceschi, T. Meunier, F. Gaillard

{"title":"Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing","authors":"B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen, R. Maurand, S. Haendler, A. Juge, E. Vincent, P. Galy, G. Ghibaudo, M. Vinet, S. de Franceschi, T. Meunier, F. Gaillard","doi":"10.1109/VLSITechnology18217.2020.9265034","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265034","url":null,"abstract":"Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T for short channel transistors, with $mathrm{I}_{mathrm{ON}} > 1mathrm{mA}mu mathrm{m}$ and $mathrm{I}_{mathrm{OFF}}$ below the equipment accuracy <1 fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (R T) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations increase on both threshold voltage $(mathrm{V}_{mathrm{TH}})$ and current gain factor $(beta)$ variabilities. Besides that, we demonstrated that the increase of $mathrm{V}_{mathrm{TH}}$ and $beta$ variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85397265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21