2020 IEEE Symposium on VLSI Technology最新文献_第10页

Surrounding Gate Vertical-Channel FET with Gate Length of 40 nm Using BEOL Compatible High-Thermal-Tolerance In-Al-Zn Oxide Channel 采用与BEOL兼容的高耐热铝锌氧化物沟道制备栅极长度为40 nm的环栅垂直沟道场效应管

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265109

H. Fujiwara, Yuta Sato, N. Saito, Tomomasa Ueda, K. Ikeda

引用次数: 3

Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-cap-free Gate Stack and Optimizing the Channel Strain 解决SiGe-pFin技术的关键挑战:翅片完整性，低dit无硅帽栅极堆栈和优化通道应变

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265035

H. Arimura, E. Capogreco, K. Wostyn, G. Eneman, L. Ragnarsson, S. Brus, S. Baudot, A. Peter, T. Schram, P. Favia, O. Richard, H. Bender, J. Mitard, N. Horiguchi

引用次数: 4

ExaNoDe: combined integration of chiplets on active interposer with bare dice in a multi-chip-module for heterogeneous and scalable high performance compute nodes ExaNoDe:将主动式中介器上的小芯片与裸骰子集成在多芯片模块中，用于异构和可扩展的高性能计算节点

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265100

Pierre-Yves Martinez, Y. Beilliard, M. Godard, D. Danovitch, D. Drouin, J. Charbonnier, P. Coudrain, A. Garnier, D. Lattard, P. Vivet, S. Chéramy, E. Guthmuller, C. F. Tortolero, V. Mengue, J. Durupt, A. Philippe, D. Dutoit

引用次数: 7

Ultra-low $p_{c}$ Extraction for Recessed and Non-Recessed Contacts: Generalized Transmission Line Model 嵌入式和非嵌入式触点的超低$p_{c}$提取:广义传输线模型

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/vlsitechnology18217.2020.9265077

Ying Wu, Haiwen Xu, Jishen Zhang, Chengkuan Wang, Zuopu Zhou, Haibo Wang, X. Gong, Y. Yeo

{"title":"Ultra-low $p_{c}$ Extraction for Recessed and Non-Recessed Contacts: Generalized Transmission Line Model","authors":"Ying Wu, Haiwen Xu, Jishen Zhang, Chengkuan Wang, Zuopu Zhou, Haibo Wang, X. Gong, Y. Yeo","doi":"10.1109/vlsitechnology18217.2020.9265077","DOIUrl":"https://doi.org/10.1109/vlsitechnology18217.2020.9265077","url":null,"abstract":"A universal transmission line model (TLM) is developed to provide an accurate extraction of specific contact resistivity <tex>$rho_{c}$</tex> for both recessed and non-recessed contacts. This new model eliminates the need for the assumption that semiconductor sheet resistance under the contact <tex>$R_{shc}$</tex> is equal to that <tex>$mathrm{in}$</tex> the contact gap region <tex>$R_{sh}$</tex> which has been used for decades and expands the application of TLM-based methods for alloyed contacts for the first time. The model was verified experimentally by applying it to directly extract <tex>$rho_{c}, R_{shc}$</tex>, and metal sheet resistance <tex>$R_{m}$</tex> of alloyed p+-GeSn contact. The change of <tex>$R_{shc}$</tex> due to alloying or recess-etching is well captured and ultra-low <tex>$rho_{c}$</tex> values of <tex>$1.0times 10^{-9}Omega-mathrm{cm}^{2}$</tex> are extracted. In contrast, conventional TLM-based methods lead to a large variation <tex>$mathrm{in}rho_{c}$</tex> extraction and miscalculate <tex>$rho_{c}$</tex> by neglecting the deviation of <tex>$R_{shc}$</tex> from <tex>$R_{sh}$</tex>.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"49 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85076863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Toward Long-coherence-time Si Spin Qubit: The Origin of Low-frequency Noise in Cryo-CMOS 走向长相干时间Si自旋量子位:低温cmos中低频噪声的来源

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/vlsitechnology18217.2020.9265013

H. Oka, T. Matsukawa, K. Kato, S. Iizuka, W. Mizubayashi, K. Endo, T. Yasuda, T. Mori

引用次数: 12

Can We Ever Get to a 100 nm Tall Library? Power Rail Design for 1nm Technology Node 我们能建一个100纳米高的图书馆吗?1nm技术节点电源导轨设计

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265022

V. Moroz, X. Lin, P. Asenov, D. Sherlekar, M. Choi, B. Cheng, S. Parikh, Po-Wen Chan, J. Lee

引用次数: 2

3D Heterogeneous Package Integration of Air/Magnetic Core Inductor: 89%-Effi- ciency Buck Converter with Backside Power Delivery Network 空气/磁芯电感器的三维异质封装集成:89%效率的Buck变换器与反向输电网络

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265045

Xiao Sun, Hesheng Lin, D. Velenis, J. Slabbekoorn, G. Talmelli, P. Bex, T. Sterken, R. Lauwereins, C. Adelmann, Andy Miller, G. van der Plas, E. Beyne

引用次数: 2

A Novel Dual Ferroelectric Layer Based MFMFIS FeFET with Optimal Stack Tuning Toward Low Power and High-Speed NVM for Neuromorphic Applications 一种新的基于双铁电层的MFMFIS效应场效应管，具有最优堆栈调谐，可用于神经形态应用的低功耗和高速NVM

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265111

T. Ali, K. Seidel, K. Kühnel, M. Rudolph, M. Czernohorsky, K. Mertens, R. Hoffmann, K. Zimmermann, U. Mühle, Johannes Müller, J. van Houdt, L. Eng

{"title":"A Novel Dual Ferroelectric Layer Based MFMFIS FeFET with Optimal Stack Tuning Toward Low Power and High-Speed NVM for Neuromorphic Applications","authors":"T. Ali, K. Seidel, K. Kühnel, M. Rudolph, M. Czernohorsky, K. Mertens, R. Hoffmann, K. Zimmermann, U. Mühle, Johannes Müller, J. van Houdt, L. Eng","doi":"10.1109/VLSITechnology18217.2020.9265111","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265111","url":null,"abstract":"A Novel MFMFIS FeFET based on dual MFM/MFIS integration in a single gate stack is reported. The external top and bottom contacts, dual ferroelectric (FE) layers, and tailored MFM/MFIS area ratio $(mathrm{A}_{mathrm{FI}})$ shows flexible stack tuning for improved FeFET performance. A tradeoff between maximized MFM voltage and weaker FET channel inversion is notable in the ID(sat) as AFI decreases. A dual FE layer enables maximized MW and fine control of its size when MFM/MFIS switching contribution is tuned through AFI change. The merits of $mathrm{A}_{mathrm{FI}}$ tuning extends to low voltage switching with maximized MW size and extremely linear current change over a wide dynamic range at high symmetry of synaptic potentiation/depression. Reliability in terms of variability, temperature effects, endurance, and retention is reported. The MFMFIS concept is thoroughly discussed with insight on optimal stack tuning for improved FeFET characteristics.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85450625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6