Mingshan Liu, V. Schlykow, J. Hartmann, J. Knoch, D. Grutzmacher, D. Buca, Qing-Tai Zhao
{"title":"Vertical Heterojunction Ge0.92 Sn0.08 /Ge GAA Nanowire pMOSFETs: Low SS of 67 mV/dec, Small DIBL of 24 mV/V and Highest Gm,ext of 870 μS/μm","authors":"Mingshan Liu, V. Schlykow, J. Hartmann, J. Knoch, D. Grutzmacher, D. Buca, Qing-Tai Zhao","doi":"10.1109/vlsitechnology18217.2020.9265090","DOIUrl":"https://doi.org/10.1109/vlsitechnology18217.2020.9265090","url":null,"abstract":"We demonstrate high performance vertical heterojunction Ge0.92Sn0.08/Ge gate-all-around (GAA) nanowire (NW) pMOSFETs enabled by a top-down approach, a self-limiting digital etching and NiGeSn metallization. Thanks to the GAA NW geometry and EOT scaling, low SS of 67 mV/dec, small DIBL of 24 mV/V, and a high ION/IOFF ratio of ~106 are achieved in the smallest NW device with a diameter down to 25 nm. Furthermore, record high Gm,ext of ~870 μS/μm and the best quality factor Q = Gm,ext/SSsat of 9.1 are obtained for all reported GeSn-based pFETs.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73445131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chien-Ping Wang, Ying-Chun Shen, Kun-Lin Liou, Y. Chueh, Y. Chih, Jonathan Chang, J. Shih, C. Lin, Y. King
{"title":"Hair-Like Nanostructure Based Ion Detector by 16nm FinFET Technology","authors":"Chien-Ping Wang, Ying-Chun Shen, Kun-Lin Liou, Y. Chueh, Y. Chih, Jonathan Chang, J. Shih, C. Lin, Y. King","doi":"10.1109/VLSITechnology18217.2020.9265084","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265084","url":null,"abstract":"A novel hair-like nanostructure incorporated a floating gate Ion-Sensitivities Field Effect Transistor (ISFET) is demonstrated for the first time. With its corresponding readout circuit embedded by 16nm FinFET technology, the proposed ion detector features high sensitivity and wide/adjustable dynamic range. Additionally, real-time detection of both pH level and sodium ion concentration on liquid samples is verified, while their noise analysis for robust and stable reading is performed.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74856740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Roth, Charlie Zhou, Mei Wong, E. Soenen, Tze-Chiang Huang, Paul Ranucci, Y. Hsu, Hung-Chih Lin, C. Kuo, Min-Jer Wang, Sheng-Yao Yang, J.R. Chu, Ting-Yu Yeh, K. Ting, A. Loke, S. Rusu, Mark Chen, F. Lee, Kevin Zhang, A. Kalnitsky
{"title":"Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors Using Integrated Passive Device and In-Package Voltage Regulator","authors":"A. Roth, Charlie Zhou, Mei Wong, E. Soenen, Tze-Chiang Huang, Paul Ranucci, Y. Hsu, Hung-Chih Lin, C. Kuo, Min-Jer Wang, Sheng-Yao Yang, J.R. Chu, Ting-Yu Yeh, K. Ting, A. Loke, S. Rusu, Mark Chen, F. Lee, Kevin Zhang, A. Kalnitsky","doi":"10.1109/VLSITechnology18217.2020.9265105","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265105","url":null,"abstract":"We demonstrate two heterogeneous solutions to improve power delivery to High-Performance Computing (HPC) processors. The scalable HPC vehicle integrates two 7nm CMOS processor chiplets, each with four ARM® Cortex®-A72 cores, that are mounted on a Chip-on-Wafer-on-Substrate (CoWoS®) silicon interposer [1]. In the first solution, Integrated Passive Device (IPD) capacitors are placed directly beneath the interposer to provide more accessible and effective supply noise decoupling. The result is 3.9% higher maximum clock frequency at a core supply of 1.135V. In the second solution, the processor is powered by a laterally mounted in-Package Voltage Regulator (PVR) built in 28nm CMOS augmented with high-per-meability on-die inductors. The processor performance provided by the buck converter-based PVR matches that by an off-package External Voltage Regulator (EVR). As processor power increases with higher core counts, PVRs with on-die inductors will be increasingly compelling for efficient system power delivery.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78765391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shute, Fumitaka Sugaya, M. Materano, T. Ali, Kati Kuehnel, Konrad Seide, U. Schroeder, T. Mikolajick, M. Tsukamoto, T. Umebayashi
{"title":"SoC compatible 1 T1 C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2","authors":"J. Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shute, Fumitaka Sugaya, M. Materano, T. Ali, Kati Kuehnel, Konrad Seide, U. Schroeder, T. Mikolajick, M. Tsukamoto, T. Umebayashi","doi":"10.1109/VLSITechnology18217.2020.9265063","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265063","url":null,"abstract":"This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2-based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ $mathrm{Hf}_{0.5}mathrm{Zr}_{0.5}mathrm{O}_{2}(mathrm{HZO}$)/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization $2mathrm{P}_{mathrm{r}} > 4vert mumathrm{C}/mathrm{cm}^{2}$, endurance> 1011 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81852157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jianguo Yang, Qingting Ding, Tiancheng Gong, Q. Luo, X. Xue, Zhaomeng Gao, Haoran Yu, Jie Yu, Xiaoxin Xu, Peng Yuan, Xiaoyan Li, L. Tai, S. Chung, H. Lv, Ming Liu
{"title":"Robust True Random Number Generator Using Stochastic Short-term Recovery of Charge Trapping FinFET for Advanced Hardware Security","authors":"Jianguo Yang, Qingting Ding, Tiancheng Gong, Q. Luo, X. Xue, Zhaomeng Gao, Haoran Yu, Jie Yu, Xiaoxin Xu, Peng Yuan, Xiaoyan Li, L. Tai, S. Chung, H. Lv, Ming Liu","doi":"10.1109/VLSITechnology18217.2020.9265048","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265048","url":null,"abstract":"In this work, we demonstrated a novel true random number generator (TRNG) utilizing stochastic short-term recovery of Charge- Trapping (CT) FinFET devices. The true random bits were generated by measuring the recovery time of CT-FinFET with a digital counter by a time-to-digital count converter (TDCC) unit. The resulting CT - TRNG circuit shows great immunity against a power noise of up to 600m V in amplitude and up to 1.5G Hz in frequency across a wide range of temperatures (-20 to 85°C). It passed all NIST 800–22 and NIST 800-90B randomness tests. We have shown this novel CT - TRNG to be the most promising high-reliability hardware security solution to date.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"6 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84094547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. B. Naik, K. Yamane, J. H. Lim, T. Y. Lee, J. Kwon, Behin Aein, N. Chung, L. Y. Hau, R. Chao, D. Zeng, Y. Otani, C. Chiang, Y. Huang, L. Pu, N. Thiyagarajah, S. Jang, W. Neo, H. Dixit, S.-K., L. C. Goh, T. Ling, J. Hwang, J. W. Ting, L. Zhang, R. Low, N. Balasankaran, C. Seet, S. Ong, J. Wong, Y. You, S. Woo, S. Siah
{"title":"A Reliable TDDB Lifetime Projection Model Verified Using 40Mb STT-MRAM Macro at Sub-ppm Failure Rate To Realize Unlimited Endurance for Cache Applications","authors":"V. B. Naik, K. Yamane, J. H. Lim, T. Y. Lee, J. Kwon, Behin Aein, N. Chung, L. Y. Hau, R. Chao, D. Zeng, Y. Otani, C. Chiang, Y. Huang, L. Pu, N. Thiyagarajah, S. Jang, W. Neo, H. Dixit, S.-K., L. C. Goh, T. Ling, J. Hwang, J. W. Ting, L. Zhang, R. Low, N. Balasankaran, C. Seet, S. Ong, J. Wong, Y. You, S. Woo, S. Siah","doi":"10.1109/VLSITechnology18217.2020.9265086","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265086","url":null,"abstract":"We report a reliable TDDB lifetime projection model using power law verified from 40Mb STT-MRAM macro at sub-ppm failure rate to realize nearly unlimited endurance for cache applications. A specially designed macro, having internal temperature control systems and capable of applying accelerated voltage at 40Mb array level with wide operating temperature range: −40~125 °C and varying pulse widths: 200~10 ns, is used for the study. We demonstrate a superior endurance performance of > 1 E 12 cycles at 1 ppm failure rate using 40Mb macro combined with SRAM -like MTJ stack with lower operating voltage at BER ~ 1 ppm at 1 0 ns write pulse.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78639096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. S. Lin, W.T. Huang, A. Huang, Y.H. Yang, Y. Hsu, S.K. Yang, Jack Liu, H.W. Tseng, Jarcle Huang, B.Y. Chou, Kevin Huang, W. Chang, Daniel Chang, C. H. Chien, H. Yeh, P. Liu, C.D. Hsieh, H. Chuang, A. Kalnitsky
{"title":"An approach to embedding traditional non-volatile memories into a deep sub-micron CMOS","authors":"C. S. Lin, W.T. Huang, A. Huang, Y.H. Yang, Y. Hsu, S.K. Yang, Jack Liu, H.W. Tseng, Jarcle Huang, B.Y. Chou, Kevin Huang, W. Chang, Daniel Chang, C. H. Chien, H. Yeh, P. Liu, C.D. Hsieh, H. Chuang, A. Kalnitsky","doi":"10.1109/VLSITechnology18217.2020.9265049","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265049","url":null,"abstract":"This work presents an example of 16nm FinFET CMOS with an embedded flash 40nm memory employing Wafer-on-Wafer (WoW) technology. Our results show comparable embedded flash performance, CMOS logic speed and power consumption comparing corresponding circuits before and after the 3D assembly. WoW integration can provide embedded flash solution for advanced CMOS nodes where no solutions currently exist. The method is also applicable for embedding other functionalities into the advanced CMOS.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"106 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88313073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Sousa, A. Chavent, V. Iurchuk, L. Vila, U. Ebels, B. Dleny, G. Di Pendina, G. Prenat, J. Langer, J. Wrona, I. Prejbeanu
{"title":"Magnetic random access memories (MRAM) beyond information storage","authors":"R. Sousa, A. Chavent, V. Iurchuk, L. Vila, U. Ebels, B. Dleny, G. Di Pendina, G. Prenat, J. Langer, J. Wrona, I. Prejbeanu","doi":"10.1109/VLSITechnology18217.2020.9265053","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265053","url":null,"abstract":"Magnetic random access memory (MRAM) is now available as embedded memory from major CMOS foundries. In this study, we demonstrated that slightly modified magnetic tunnel junctions than those used in conventional STT -MRAM can be used for multifunctional purposes, namely magnetic field sensing and RF oscillators. For that, the F eCoB storage layer thickness in the perpendicular anisotropy magnetic stack was adjusted to 1.3-1.4 nm, closer to the transition region from perpendicular to in-plane anisotropy. Two possible configurations of magnetic field sensing using the same stack can be used, achieving high sensitivity in small field range or lower sensitivity in large field range. Additionally, RF oscillator GHz detection and generation were also demonstrated. Further applications of this multifunctional stack can be envisioned including non-volatile and reprogrammable logic, special functions such as random number generator and memristors.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"7 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88557481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jie Deng, U. Roh, Jerry Bao, Youseok Suh, Jihong Choi, Ying Chen, Vicki Lin, Jason Cheng, Zhimin Song, M. Cai, L. Ge, Gary Chen, Leo Kim, Hao Wang, S. Song, Deepak Kumar Sharma, Xiao yong Wang, Byungmoo Song, Y. Y. Masuoka, Kwon Lee, Sungwon Kim, Jinkyu Lee, Hyejun Jin, Venu Boynapalli, Rajagopal Narayanan, P. Pénzes, G. Nallapati, C. Chidambaram
{"title":"5G and AI Integrated High Performance Mobile SoC Process-Design Co-Development and Production with 7nm EUV FinFET Technology","authors":"Jie Deng, U. Roh, Jerry Bao, Youseok Suh, Jihong Choi, Ying Chen, Vicki Lin, Jason Cheng, Zhimin Song, M. Cai, L. Ge, Gary Chen, Leo Kim, Hao Wang, S. Song, Deepak Kumar Sharma, Xiao yong Wang, Byungmoo Song, Y. Y. Masuoka, Kwon Lee, Sungwon Kim, Jinkyu Lee, Hyejun Jin, Venu Boynapalli, Rajagopal Narayanan, P. Pénzes, G. Nallapati, C. Chidambaram","doi":"10.1109/VLSITechnology18217.2020.9265074","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265074","url":null,"abstract":"We report on Qualcomm® Snapdragon™ 765 mobile Platform and world's first integrated 5G platform supporting both mmWave and sub-6 using industry-leading 7nm EUV FinFET technology. Snapdragon 765 unites 5G and AI to power select premium-tier experiences on a global scale. Snapdragon 765 exhibits 20% improvement in performance and 35% lower power consumption over its predecessor Snapdragon 730 (8nm FinFET) thanks to device performance boost with new technology integration feature (MDB), power-perf efficient design architecture enabled by dual poly pitch process, and low voltage logic/memory operation through process-design co-development. Further process-design co-optimization reduces CPU Vmin by 80mV, enabling premium-tier performance experience with integrated 5G and AI mobile SOC platform.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89706550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Cavalcante, C. Fenouillet-Beranzer, P. Batude, X. Garros, X. Federspiel, J. Lacord, S. Kerdilès, A. Royet, P. Acosta-Alba, O. Rozeau, V. Barral, F. Arnaud, N. Planes, P. Sassoulas, E. Ghegin, R. Beneyton, M. Grégoire, O. Weber, C. Guérin, L. Arnaud, S. Moreau, R. Kies, G. Romano, N. Rambal, A. Magalhaes, G. Ghibaudo, J-P. Colinag, M. Vinet, F. Andrieu
{"title":"28nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D Sequential Integration: yield and reliability analysis","authors":"C. Cavalcante, C. Fenouillet-Beranzer, P. Batude, X. Garros, X. Federspiel, J. Lacord, S. Kerdilès, A. Royet, P. Acosta-Alba, O. Rozeau, V. Barral, F. Arnaud, N. Planes, P. Sassoulas, E. Ghegin, R. Beneyton, M. Grégoire, O. Weber, C. Guérin, L. Arnaud, S. Moreau, R. Kies, G. Romano, N. Rambal, A. Magalhaes, G. Ghibaudo, J-P. Colinag, M. Vinet, F. Andrieu","doi":"10.1109/VLSITechnology18217.2020.9265075","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265075","url":null,"abstract":"For the first time, the thermal stability of a 28nm FDSOI CMOS technology is evaluated with yield measurements (5Mbit dense SRAM and 1 Million Flip- flops). It is shown that 500°C 2h thermal budget can be applied on a digital 28nm circuit including State-Of- The-Art Cu/ULK BEOL without yield nor reliability degradation. These results pave the way to the introduction of BEOL between tiers in 3D sequential integration while the thermal budget allowed for the top tier is sufficient to lead to high performance device.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76848447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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