{"title":"The Future of Compute: How the Data Transformation is Reshaping VLSI","authors":"M. Mayberry","doi":"10.1109/VLSITechnology18217.2020.9265068","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265068","url":null,"abstract":"The digital transformation continues to gain momentum, as businesses offer consumers increasingly distributed services, and industry pursues improvements across the extent of the electronics ecosystem. This transformation is characterized by continued strong demand for compute at all points in the network - at the core, the edge, and at the endpoints. Data continues to grow at an exponential rate and not only drives the compute requirements, but also requires efficient solutions for movement and storage of data that is critical for overall performance. From device to cloud, new applications and use cases are continuously emerging. This transformation demands that we adapt our thinking and move from a hardware/program centric to a data/information centric approach, and to embrace new ways to compute. To keep pace in this dynamic environment, Moore's Law and its impact have become more relevant than ever. The continued scaling of dimensions, materials and devices drives a renewed focus on the fundamental physics of devices and materials, while novel architecture schemes and system design innovation motivate a more comprehensive understanding of large-scale integration at all levels of the system.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"51 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79391285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Fenouillet-Béranger, L. Brunet, P. Batude, L. Brevard, X. Garros, T. M. Frutuoso, M. Cassé, J. Lugo, J. Lacord, D. Bosch, N. Bernard, A. Magalhaes-Lucas, M. Ribotta, B. Sklénard, F. Milési, R. Kies, G. Romano, P. Acosta-Alba, S. Kerdilès, A. Tavernier, C. Vizioz, P. Besson, R. Gassilloud, J. Kanyandekwe, D. Cooper, V. Lapras, W-H. Kim, Y. Sasaki, S. Oh, P. Kang, S.W. Lee, H. Na, J. Arcamone, F. Andrieu
{"title":"First demonstration of low temperature $(leq 500^{circ}mathrm{C})$ CMOS devices featuring functional RO and SRAM bitcells toward 3D VLSI integration","authors":"C. Fenouillet-Béranger, L. Brunet, P. Batude, L. Brevard, X. Garros, T. M. Frutuoso, M. Cassé, J. Lugo, J. Lacord, D. Bosch, N. Bernard, A. Magalhaes-Lucas, M. Ribotta, B. Sklénard, F. Milési, R. Kies, G. Romano, P. Acosta-Alba, S. Kerdilès, A. Tavernier, C. Vizioz, P. Besson, R. Gassilloud, J. Kanyandekwe, D. Cooper, V. Lapras, W-H. Kim, Y. Sasaki, S. Oh, P. Kang, S.W. Lee, H. Na, J. Arcamone, F. Andrieu","doi":"10.1109/VLSITechnology18217.2020.9265092","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265092","url":null,"abstract":"For the first time FDSOI CMOS transistors with Si- monocrystalline channel have been fabricated at a temperature below 500°C. High performance PMOS $(mathrm{Ion}=450mu mathrm{A}/mu mathrm{m}$ (V dd −0.9V) @ $mathrm{Ioff}=-2mathrm{nA}/mu mathrm{mLg}=35mathrm{nm})$ with low overlap capacitance $(0.46mathrm{fF}/mu mathrm{m}$ per device), low gate resistance $(10Omega)$ at Low Temperature (L T) enables to achieve good RF Figure-Of-Merit (FOM) with Fmax values up to 170GHz. In addition, we demonstrate for the first time the full functionality of Ring Oscillators (RO) and SRAM bitcells processed at 500°C, paving the way for a high-performance 3D sequential CMOS integration.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"44 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84628337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada
{"title":"1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy","authors":"X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada","doi":"10.1109/VLSITechnology18217.2020.9265046","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265046","url":null,"abstract":"1.5x energy-efficient and 1.4x operation-speed, nonvolatile via-switch (VS) FPGA with atom switch and a-Si/SiN/a-Si varistor is demonstrated in a 65nm-node for various basic applications. For rapid and low-cost migration from VS-FPGA to ASIC, “hard-via” to replace VS with “ON”, named VS-copy (VSC), is newly proposed. The VSC-ASIC is fabricated by sharing all the photo masks with VS-FPGA excepting one via mask revise and three VS masks skip, realizing an exact design copy with minimum NRE cost and TAT. The VS-FPGA equipped with the VSC gives energy-efficient edge device, e.g., for up-to-date AI inference algorithms, covering a wide range of chip volume with extremely low cost.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"9 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81597969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chih-Chao Yang, Ping-Yi Hsieh, Po-Han Chen, Tung-Ying Hsieh, Po-Tsang Huang, Yu-Ting Lin, C. Shen, J. Shieh, Da-Chiang Chang, W. Yeh, Meng-Chyi Wu, Yi‐Hsien Lee
{"title":"Ultrahigh responsivity and tunable photogain BEOL compatible $mathrm{MoS}_{2}$ phototransistor array for monolithic 3D image sensor with block-level sensing circuits","authors":"Chih-Chao Yang, Ping-Yi Hsieh, Po-Han Chen, Tung-Ying Hsieh, Po-Tsang Huang, Yu-Ting Lin, C. Shen, J. Shieh, Da-Chiang Chang, W. Yeh, Meng-Chyi Wu, Yi‐Hsien Lee","doi":"10.1109/VLSITechnology18217.2020.9265017","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265017","url":null,"abstract":"A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3} mathrm{A}/mathrm{W})$ and tunable photogain (102~105) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"2 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88096758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chen Sun, Jie Liang, Haiwen Xu, E. Kong, B. Nguyen, A. Vandooren, W. Schwarzenbach, C. Maleville, V. Barral, R. Berthelon, O. Weber, F. Arnaud, A. Thean, X. Gong
{"title":"Enabling UTBB Strained SOI Platform for Co-integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-like Device Architecture","authors":"Chen Sun, Jie Liang, Haiwen Xu, E. Kong, B. Nguyen, A. Vandooren, W. Schwarzenbach, C. Maleville, V. Barral, R. Berthelon, O. Weber, F. Arnaud, A. Thean, X. Gong","doi":"10.1109/VLSITechnology18217.2020.9265070","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265070","url":null,"abstract":"For the first time, ion implant was used to partially relax the tensile strain by half in the fully-depleted (FD) strained SOI (SSOl) so that SiGe pFETs with a higher compressive strain can be realized at a fixed Ge composition. This enables the co-integration of highly tensile-strained Si nFETs and compressive-strained SiGe pFETs on the same substrate, achieving significant improvement in electrical performance over the unstrained counterpart verified by both experiment and simulation results. We also propose a Comb-like strained SOI architecture to further boost RF performance, demonstrating peak $G_{mathrm{m}}$ improved by 47% over unstrained n-type FinFET SOI, as well as an improvement of 22% and 36% for $f_{mathrm{T}}$ and $f_{max}$, respectively, over n-type FinFETs SSOI.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"42 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86296411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Ichihara, Kunifumi Suzuki, H. Kusai, K. Ariyoshi, Keisuke Akari, Keisuke Takano, K. Matsuo, Y. Kamiya, Kota Takahashi, Hidenori Miyazawa, Y. Kamimuta, K. Sakuma, M. Saitoh
{"title":"Re-examination of Vth Window and Reliability in HfO2 FeFET Based on the Direct Extraction of Spontaneous Polarization and Trap Charge during Memory Operation","authors":"R. Ichihara, Kunifumi Suzuki, H. Kusai, K. Ariyoshi, Keisuke Akari, Keisuke Takano, K. Matsuo, Y. Kamiya, Kota Takahashi, Hidenori Miyazawa, Y. Kamimuta, K. Sakuma, M. Saitoh","doi":"10.1109/VLSITechnology18217.2020.9265055","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265055","url":null,"abstract":"We re-examine the dominant factors of the memory window (MW) and reliability of HfO<inf>2</inf> FeFET using a new technique to extract both spontaneous polarization <tex>$(mathrm{P}_{mathrm{s}})$</tex> and interface trap charges <tex>$(mathrm{Q}_{mathrm{t}})$</tex> by one-time current measurement of an FeFET during the memory operation. FeFET characteristics are strongly affected by unstable <tex>$mathrm{Q}_{t}$</tex> (unrelated to ferroelectric) which causes <tex>$mathrm{V}_{mathrm{th}}$</tex> instability just after programming, and stable <tex>$mathrm{Q}_{1}$</tex> which compensates most of electric(E)- field generated by <tex>$mathrm{P}_{mathrm{s}}$</tex>. Stable <tex>$mathrm{Q}_{mathrm{t}}$</tex> is coupled to <tex>$mathrm{P}_{mathrm{s}}$</tex> with constant ratio (~90%), and reduce MW to the value much lower than the coercive voltage <tex>$(mathrm{V}_{mathrm{c}})$</tex> limitation. Unlike the conventional model, <tex>$mathrm{P}_{mathrm{s}}$</tex> increase and stabilization are still effective to improve MW and retention, respectively. During cycling, MW is degraded by <tex>$Delta mathrm{P}_{mathrm{s}}$</tex> reduction as well as the increase of the compensation ratio <tex>$(Delta mathrm{Q}_{mathrm{t}}/Delta mathrm{P}_{mathrm{s}})$</tex> which can be mitigated by suppressing charge injection/ejection via interfacial <tex>$mathrm{SiO}_{2}$</tex>.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"36 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80103833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. C. Wu, W. Kim, K. Garello, F. Yasin, G. Jayakumar, S. Couet, R. Carpenter, S. Kundu, S. Rao, D. Crotti, J. van Houdt, G. Groeseneken, G. Kar
{"title":"Deterministic and field-free voltage-controlled MRAM for high performance and low power applications","authors":"Y. C. Wu, W. Kim, K. Garello, F. Yasin, G. Jayakumar, S. Couet, R. Carpenter, S. Kundu, S. Rao, D. Crotti, J. van Houdt, G. Groeseneken, G. Kar","doi":"10.1109/VLSITechnology18217.2020.9265057","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265057","url":null,"abstract":"We propose a deterministic VCMA writing concept that allows exclusion of the pre-read which is required in conventional VCMA write scheme. We apply it on 400°C compatible pMTJ devices with high TMR 246% and retention $Delta=54$ and demonstrate a genuine ns-scale write speed. Furthermore, we realize reliable 1.1 GHz external field-free VCMA switching with 20fJ write energy by integrating a magnetic hard mask as the in-plane magnetic field generator. An endurance of more than $10^{10}$ cycles is achieved. Our results address the fundamental write operation challenges of the voltage-controlled MRAM technologies.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88352246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Y. Lee, K. Yamane, J. Kwon, V. B. Naik, Y. Otani, D. Zeng, J. H. Lim, K. Sivabalan, C. Chiang, Y. Huang, S. Jang, L. Y. Hau, R. Chao, N. Chung, W. Neo, K. Khua, N. Thiyagarajah, T. Ling, L. C. Goh, J. Hwang, L. Zhang, R. Low, N. Balasankaran, F. Tan, J. Wong, C. Seet, J. W. Ting, S. Ong, Y. You, S. Woo, S. Siah
{"title":"Fast Switching of STT-MRAM to Realize High Speed Applications","authors":"T. Y. Lee, K. Yamane, J. Kwon, V. B. Naik, Y. Otani, D. Zeng, J. H. Lim, K. Sivabalan, C. Chiang, Y. Huang, S. Jang, L. Y. Hau, R. Chao, N. Chung, W. Neo, K. Khua, N. Thiyagarajah, T. Ling, L. C. Goh, J. Hwang, L. Zhang, R. Low, N. Balasankaran, F. Tan, J. Wong, C. Seet, J. W. Ting, S. Ong, Y. You, S. Woo, S. Siah","doi":"10.1109/VLSITechnology18217.2020.9265027","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265027","url":null,"abstract":"We demonstrate less than 10 ns write speed and read access for 40Mb embedded MRAM (eMRAM) macro covering high temperature up to 125°C. The macro shows un-powered data retention of 10 second at 125°C and the capability of achieving 1012 cycles endurance and 5 ns read time. Our study indicates that MTJ stack engineering and MTJ CD optimization are the two critical factors to achieve the suppression of bit error rate (BER) ballooning and 0.5x Ic scaling for fast switching.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"58 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88426607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chia-Yu Wang, Meng-Chun Shih, Chih-Hui Weng, Chia-Hsiang Chen, Chih-Yang Chang, Wayne Wang, T. Chiang, Arthur Hung, H. Chuang, W. Gallagher
{"title":"Reliability Demonstration of Reflow Qualified 22nm STT -MRAM for Embedded Memory Applications","authors":"Chia-Yu Wang, Meng-Chun Shih, Chih-Hui Weng, Chia-Hsiang Chen, Chih-Yang Chang, Wayne Wang, T. Chiang, Arthur Hung, H. Chuang, W. Gallagher","doi":"10.1109/VLSITechnology18217.2020.9265054","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265054","url":null,"abstract":"In this paper, we thoroughly demonstrate the reliability of reflow qualified embedded S TT - MRAM integrated on 22nm technology. We show that STT-MRAM is capable of 1E5 endurance cycles across temperature (-40, 25 and 125°C) with extremely low fail bit rates (mean 0.04 ppm for −40°C) and can pass 1M cycle endurance using an enhanced process. Bit error rates (BERs) post three cycles of solder reflow at 260°C are below 1 ppm for both parallel (P) and anti-parallel (AP) storage states. Due to the associated high energy barrier for flipping states, chips can meet a very high retention lifetime spec (>200°C at 10yrs, BER 1 ppm) with a large margin. The balance of retention performance between the two states can be adjusted in an optimized process. In addition, we investigate the impact of magnetic field applied at tilted angles and report standby magnetic field immunity can reach 600 Oe at 125°C for 10 years for fields tilted 60 degrees from parallel to the die surface. Magnetic shields are demonstrated to sustain data exposed to perpendicular fields up to 3.5k Oe at 25°C for 100 hours.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"95 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81832590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Grenouillet, T. Francois, J. Coignus, S. Kerdilès, N. Vaxelaire, C. Carabasse, F. Mehmood, S. Chevalliez, C. Pellissier, F. Triozon, F. Mazen, G. Rodriguez, T. Magis, V. Havel, S. Slesazeck, F. Gaillard, U. Schroeder, T. Mikolajick, E. Nowak
{"title":"Nanosecond Laser Anneal (NLA) for Si-implanted HfO2 Ferroelectric Memories Integrated in Back-End Of Line (BEOL)","authors":"L. Grenouillet, T. Francois, J. Coignus, S. Kerdilès, N. Vaxelaire, C. Carabasse, F. Mehmood, S. Chevalliez, C. Pellissier, F. Triozon, F. Mazen, G. Rodriguez, T. Magis, V. Havel, S. Slesazeck, F. Gaillard, U. Schroeder, T. Mikolajick, E. Nowak","doi":"10.1109/VLSITechnology18217.2020.9265061","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265061","url":null,"abstract":"10nm Si-implanted HfO<inf>2</inf> is demonstrated to be ferroelectric for the first time when integrated in a Back- End-Of - Line (BEOL) 130nm CMOS. Scaled <tex>$.28mu mathrm{m}^{2}$</tex>. capacitors demonstrate excellent endurance (10<sup>9</sup> cycles measured at 4 V, extrapolated to be 10<sup>12</sup> at 3V), with tight coercive field distributions at wafer scale and excellent data retention at 85°C. To extend the ferroelectric BEOL compatibility of 10nm or thinner HfO<inf>2</inf>- based films, but also to understand their crystallization dynamics, nanosecond laser anneal is demonstrated to be very appealing, even for undoped HfO<inf>2</inf>.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"39 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87122208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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