T. Y. Lee, K. Yamane, J. Kwon, V. B. Naik, Y. Otani, D. Zeng, J. H. Lim, K. Sivabalan, C. Chiang, Y. Huang, S. Jang, L. Y. Hau, R. Chao, N. Chung, W. Neo, K. Khua, N. Thiyagarajah, T. Ling, L. C. Goh, J. Hwang, L. Zhang, R. Low, N. Balasankaran, F. Tan, J. Wong, C. Seet, J. W. Ting, S. Ong, Y. You, S. Woo, S. Siah
{"title":"STT-MRAM快速交换实现高速应用","authors":"T. Y. Lee, K. Yamane, J. Kwon, V. B. Naik, Y. Otani, D. Zeng, J. H. Lim, K. Sivabalan, C. Chiang, Y. Huang, S. Jang, L. Y. Hau, R. Chao, N. Chung, W. Neo, K. Khua, N. Thiyagarajah, T. Ling, L. C. Goh, J. Hwang, L. Zhang, R. Low, N. Balasankaran, F. Tan, J. Wong, C. Seet, J. W. Ting, S. Ong, Y. You, S. Woo, S. Siah","doi":"10.1109/VLSITechnology18217.2020.9265027","DOIUrl":null,"url":null,"abstract":"We demonstrate less than 10 ns write speed and read access for 40Mb embedded MRAM (eMRAM) macro covering high temperature up to 125°C. The macro shows un-powered data retention of 10 second at 125°C and the capability of achieving 1012 cycles endurance and 5 ns read time. Our study indicates that MTJ stack engineering and MTJ CD optimization are the two critical factors to achieve the suppression of bit error rate (BER) ballooning and 0.5x Ic scaling for fast switching.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"58 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Fast Switching of STT-MRAM to Realize High Speed Applications\",\"authors\":\"T. Y. Lee, K. Yamane, J. Kwon, V. B. Naik, Y. Otani, D. Zeng, J. H. Lim, K. Sivabalan, C. Chiang, Y. Huang, S. Jang, L. Y. Hau, R. Chao, N. Chung, W. Neo, K. Khua, N. Thiyagarajah, T. Ling, L. C. Goh, J. Hwang, L. Zhang, R. Low, N. Balasankaran, F. Tan, J. Wong, C. Seet, J. W. Ting, S. Ong, Y. You, S. Woo, S. Siah\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265027\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate less than 10 ns write speed and read access for 40Mb embedded MRAM (eMRAM) macro covering high temperature up to 125°C. The macro shows un-powered data retention of 10 second at 125°C and the capability of achieving 1012 cycles endurance and 5 ns read time. Our study indicates that MTJ stack engineering and MTJ CD optimization are the two critical factors to achieve the suppression of bit error rate (BER) ballooning and 0.5x Ic scaling for fast switching.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"58 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265027\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265027","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast Switching of STT-MRAM to Realize High Speed Applications
We demonstrate less than 10 ns write speed and read access for 40Mb embedded MRAM (eMRAM) macro covering high temperature up to 125°C. The macro shows un-powered data retention of 10 second at 125°C and the capability of achieving 1012 cycles endurance and 5 ns read time. Our study indicates that MTJ stack engineering and MTJ CD optimization are the two critical factors to achieve the suppression of bit error rate (BER) ballooning and 0.5x Ic scaling for fast switching.